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- Project Description (00:00, 1 January 1970)
- Andres Upegui, Prof (00:00, 1 January 1970)
- Yann Thoma, Prof (00:00, 1 January 1970)
- Eduardo Sanchez, Prof (00:00, 1 January 1970)
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- Piotr Amrozik, MSc (00:00, 1 January 1970)
- Adam Piotrowski, MSc (00:00, 1 January 1970)
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- GCC Internals, Intermediate Representations (00:00, 1 January 1970)
- HLL-to-VHDL Conversion Templates (00:00, 1 January 1970)
- Intermediate Representations (00:00, 1 January 1970)
- State of The Art (00:00, 1 January 1970)
- C2VHDL others (00:00, 1 January 1970)