HLL-to-VHDL Conversion Templates

HLL Expression

VHDL Expression

Remarks

variables representation

unsigned integer variable


generic (DATA_SIZE: natural := 32);
signal : std_logic_vector (DATA_SIZE-1 downto 0);

signed integer variable


generic (DATA_SIZE: natural := 32);
??

floating point variable


generic (DATA_SIZE: natural := 32);
??

integer arithmetic operations

floating point arithmetic operations