From REuP Project
Revision as of 07:35, 3 March 2011; view current revision
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| HLL Expression
| VHDL Expression
| Remarks
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variables representation
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unsigned integer variable
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| generic (DATA_SIZE: natural := 32);
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signal : std_logic_vector (DATA_SIZE-1 downto 0);
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signed integer variable
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| generic (DATA_SIZE: natural := 32);
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??
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floating point variable
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| generic (DATA_SIZE: natural := 32);
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??
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integer arithmetic operations
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floating point arithmetic operations
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floating point library specification
