HLL-to-VHDL Conversion Templates

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-=HLL to VHDL Conversion Templates= 
{| border="1" {| border="1"
|align="center"|'''HLL Expression''' |align="center"|'''HLL Expression'''
Line 5: Line 4:
|align="center"|'''Remarks''' |align="center"|'''Remarks'''
|+ |+
-|align="center"|''variables representation''+|align="center"|'''variables representation'''
| |
| |
|+ |+
-|''integer variable''+|align="right"|''unsigned integer variable''
| |
{| {|
Line 18: Line 17:
| |
|+ |+
-|floating point variable+|align="right"|''signed integer variable''
 +|
 +{|
 +|''generic'' (DATA_SIZE: natural := 32);
 +|+
 +|''??''
 +|}
 +|
 +|+
 +|align="right"|''floating point variable''
 +|
 +{|
 +|''generic'' (DATA_SIZE: natural := 32);
 +|+
 +|''??''
 +|}
 +|
 +|+
 +|align="center"|'''integer arithmetic operations'''
 +|
 +|
 +|+
 +|align="center"|'''floating point arithmetic operations'''
| |
| |
|+ |+
|} |}

Revision as of 10:28, 20 January 2011

HLL Expression VHDL Expression Remarks
variables representation
unsigned integer variable
generic (DATA_SIZE: natural := 32);
signal : std_logic_vector (DATA_SIZE-1 downto 0);
signed integer variable
generic (DATA_SIZE: natural := 32);
??
floating point variable
generic (DATA_SIZE: natural := 32);
??
integer arithmetic operations
floating point arithmetic operations
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