Presentations
From REuP Project
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| [[Media:REuP_idea.pdf|Introduction to REuP project]] | [[Media:REuP_idea.pdf|Introduction to REuP project]] | ||
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| + | [[Media:REuP_-_MIXDES_-_HiPEAC_-_2010_-_Presentation.pdf|Instructionless processor architecture using dynamically reconfigurable logic]] | ||
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| + | [[Media:latency_hiding.pdf|Latency Hiding by Multicontext Reconfiguration]] | ||
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| + | [[Media:gcc-gimple.pdf|Introduction to Gimple IR]] | ||
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| + | [[Media:gcc-rtl.pdf|Introduction to RTL IR]] | ||
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| + | [[Media:Loops_in_C_–_compilation_stages_in_GCC_KP.pdf|Loops in C – compilation stages in GCC – code in VHDL]] | ||
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| + | [[Media:53_BSDCan2008ChrisLattnerBSDCompiler.pdf|LLVM and Clang: Next Generation Compiler Technology by Chris Lattner]] | ||
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| + | [[Media:LLVM-ELC2009.pdf|Understanding and writing an LLVM compiler back-end by Bruno Cardoso Lopes, ELC 2009]] | ||
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| + | [[Media:Fosdem09-g3dllvm.pdf|LLVM + Gallium3D: Mixing a Compiler With a Graphics Framework by Stéphane Marchesin, FOSDEM 2009]] | ||
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| + | [[Media:Tricore-llvm-slides.pdf|Design and Implementation of a TriCore Backend for the LLVM Compiler Framework by Christoph Erhardt]] | ||
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| + | [[Media:Datapath_synthesis.pdf|Datapath Synthesis]] | ||
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| + | [[Media:Syscall.pdf|System calls]] | ||
Current revision
Instructionless processor architecture using dynamically reconfigurable logic
Latency Hiding by Multicontext Reconfiguration
Loops in C – compilation stages in GCC – code in VHDL
LLVM and Clang: Next Generation Compiler Technology by Chris Lattner
Understanding and writing an LLVM compiler back-end by Bruno Cardoso Lopes, ELC 2009
LLVM + Gallium3D: Mixing a Compiler With a Graphics Framework by Stéphane Marchesin, FOSDEM 2009
Design and Implementation of a TriCore Backend for the LLVM Compiler Framework by Christoph Erhardt
