State of The Art
From REuP Project
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| [[Papers]] | [[Papers]] | ||
| - | [[Interesting Links | + | [[Interesting Links]] |
| [[Presentations]] | [[Presentations]] | ||
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| + | [[Intermediate Representations]] | ||
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| + | [[HLL-to-VHDL Conversion Templates]] | ||
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| + | [[C2VHDL others]] | ||
