State of The Art
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| - | ===Research Issues in Operating Systems for Reconfigurable Computing=== | + | [[Papers]] |
| - | * Authors: Grant B. Wigley and David A. Kearney | + | |
| - | * This paper appears in: In Proceedings of the International Conference on Engineering of Reconfigurable System and Algorithms(ERSA) | + | |
| - | * Year: 2002 | + | |
| - | * Abstract: As the number of system gates available on reconfigurable platforms increase beyond 20 million, the issue of the management of these resources and their sharing among may applications and users will become more of a concern. In this paper we describe the research issues for managing these resources in an operating system for a reconfigurable computer. We also detail a feasible set of components for the operating system and a feasible software architecture We show there is no current operating system implementation with these components. We propose a number of performance metrics which we believe are important measures of the quality of an operating system implementation. These include fragmentation of area, algorithm performance and application performance. We complete the paper with a status report on our implementation of an operating system for a reconfigurable computer. | + | |
| - | * Our comments: | + | |
| - | :[[Research Issues in Operating Systems for Reconfigurable Computing|Download]] | + | |
| - | ===ReConfigME: A Detailed Implementation of an Operating System for Reconfigurable Computing=== | + | [[Interesting Links]] |
| - | * Authors: Grant Wigley, David Kearney and Mark Jasiunas | + | |
| - | * This paper appears in: Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International Issue Date : 25-29 April 2006 On page(s): 8 pp. | + | |
| - | * ISBN: 1-4244-0054-6 | + | |
| - | * Year: 2006 | + | |
| - | * Abstract: Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. However, developing applications that share a device is difficult as the current design flow assumes the exclusive use of the FPGA resources. As a consequence, the designer must ensure that resources have been allocated for all possible combinations of loaded applications at design time. If the sequence of application loading and unloading is not known in advance, all resource allocation cannot be performed at design time because the availability of resources changes dynamically. In this paper, we present an implementation of an operating system that has the ability to share its FPGA resources dynamically among multiple executing applications. | + | |
| - | * Our comments: | + | |
| - | :[[ReConfigME: A Detailed Implementation of an Operating System for Reconfigurable Computing|Download]] | + | |
| - | ===Operating Systems for FPGA Based Computers and Their Memory Management=== | + | [[Presentations]] |
| - | * Authors: Klaus Danne | + | |
| - | * Year: 2004 | + | |
| - | * Abstract: We introduce the concept of an operating system for platforms that consist beside memory and peripheral devices of FPGAs as the only computational resource. Applications can be developed independent from each other and due to device drivers with little dependency on the platform. The OS supports the multitasking execution of applications using static as well as dynamic resource assignment. A main focus of the paper is the management of the resource memory. Memory management as part of the OS is introduced which allows multiple tasks to access the same memory banks using virtual addressing and dynamic memory allocation. Access conflicts are solved by a priority based scheduling. Since no microprocessor is part of the system, the entire OS including its memory management is executed on the FPGAs. | + | |
| - | * Our comments: | + | |
| - | :[[Operating Systems for FPGA Based Computers and Their Memory Management|Download]] | + | |
| - | ===An Adaptable Task Manager for Reconfigurable Architecture Kernels=== | + | [[Intermediate Representations]] |
| - | * Authors: Yuriy Shiyanovskii, Francis Wolff, Chris Papachristou, Dan Weyer | + | |
| - | * This paper appears in: Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on | + | |
| - | * Year: 2009 | + | |
| - | * Abstract: Self-reconfigurable hardware is a new emerging technology which will enable adaptation of computing systems to changing environments.This paper deals with the design of architecture kernels for an autonomous on-board system and the development of an adaptation manager for real-time scheduling of the reconfigurable hardware fabric.Our approach employs a reconfigurable computer architecture with two key layers: the adaptation manager and the real time configuration kernel. This provides significant advantages in terms of flexibility, scalability, cost, and compatibility with embedded technology. Some preliminary results are presented. | + | |
| - | * Our comments: | + | |
| - | :[[An Adaptable Task Manager for Reconfigurable Architecture Kernels|Download]] | + | |
| - | ===VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip=== | + | [[HLL-to-VHDL Conversion Templates]] |
| - | * Authors: Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, Deming Chen | + | |
| - | * This paper appears in: Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific | + | |
| - | * Year: 2008 | + | |
| - | * ISBN: 978-1-4244-1921-0 | + | |
| - | * Description: Zalaczony artykul przedstawia cos podobnego do tego, co chcemy zrealizowac, choc troche innego w koncepcji - application-specific multicores. | + | |
| - | * Abstract: Billions of devices on a chip is around the corner and the trend of deep submicron (DSM) technology scaling will continue for at least another decade. Meanwhile, designers also face severe on-chip parameter variations, soft/hard errors, and high leakage power. How to use these billions of devices to deliver power-efficient, high-performance, and yet error-resilient computation is a challenging task. In this paper, we attempt to demonstrate some of our perspectives to address these critical issues. We elaborate on variation-aware synthesis, holistic error modeling, reliable multicore, and synthesis for application-specific multicore. We also present some of our insights for future reliable computing. | + | |
| - | * Our comments: | + | |
| - | :[[VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip|Download]] | + | |
| - | ===A Unified Hardware/Software Runtime Environment for FPGABased Reconfigurable Computers using BORPH=== | + | [[C2VHDL others]] |
| - | * Authors: Hayden KwokHay So, Artem Tkachenko and Robert Brodersen | + | |
| - | * This paper appears in: Hardware/Software Codesign and System Synthesis, 2006. CODES+ISSS '06. Proceedings of the 4th International Conference | + | |
| - | * Year: 2006 | + | |
| - | * Abstract: This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a homogeneous UNIX interface for both software and hardware processes. Hardware processes inherit the same level of service from the kernel, such as file system support, as typical UNIX software processes. Hardware and software components of a design therefore run as hardware and software processes within BORPH's run-time environment. The familiar and language independent UNIX kernel interface facilitates easy design reuse and rapid application development. Performance of our current implementation and our experience with developing a real-time wireless digital signal processing system based on BORPH will be presented. | + | |
| - | * Our comments: | + | |
| - | :[[A Unified Hardware/Software Runtime Environment for FPGABased Reconfigurable Computers using BORPH|Download]] | + | |
| - | + | ||
| - | ===Generating the Communications Infrastructure for Module-based Dynamic Reconfiguration of FPGAs=== | + | |
| - | ** Authors: Shannon Koh | + | |
| - | ** Year: 2003 | + | |
| - | ** File: [[Media:Phdkoh.pdf|download]] | + | |
| - | ** Description: Po krotce mowiac, praca dotyczy opracowania narzedzi i metodologii (COMMA design flow opartej na Early Access Partial Reconfiguration Tool Flow) wspierajacych synteze ukladow wykorzystujacych modulowa rekonfiguracje dynamiczna na wspoczesne uklady rekonfigurowalne XILINX'a (rodzina Spartan-4) i jednoczesnie wspolpracujace z dostepnymi narzedziami producenta. Glowny nacisk w pracy polozony zostal na generacje i optymalizacje polaczen pomiedzy modulami dynamicznie rekonfigurowalnymi. Zaproponowane podejscie umozliwia zachowanie takich paramterow projektu jak np. ograniczenia czasowe, przy jednoczesnym spadku czasu dynamicznej rekonfiguracji do okolo 64% (w porownaniu do zastosowania dostepnych komercyjnie narzedzi). Autor w pracy implementuje model Brebnera ("fixed wiring harness" model), a tazke algorytm greedy'ego do łączenia grafow wsparte, rozwiniete czy tez nawet zastapione przez metode dynamicznego programowania. | + | |
| - | + | ||
| - | ===The MOLEN Polymorphic Processor=== | + | |
| - | ** S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov, E. Moscu Panainte | + | |
| - | ** Year: 2006 | + | |
| - | ** File: [[Media:Molen.pdf|download]] | + | |
| - | ** Description: | + | |
| - | + | ||
| - | ===Custom Processor Design Using NISC: A Case-Study on DCT algorithm=== | + | |
| - | ** Bita Gorjiara, Daniel Gajski | + | |
| - | ** Year: 2005 | + | |
| - | ** File: [[Media:Nisc.pdf|download]] | + | |
| - | ** Description: No-Instruction-Set-Computers (NISCs) that eliminate the instruction abstraction by compiling programs directly to a given datapath. | + | |
| - | + | ||
| - | ===GENERIC and GIMPLE: A New Tree Representation for Entire Functions=== | + | |
| - | ** Authors: Jason Merrill | + | |
| - | ** Year: 2003 | + | |
| - | ** File: [[Media:GENERIC_and_GIMPLE.pdf|download]] | + | |
| - | ** Description: The tree SSA project requires a tree representation of functions for the optimizers to operate on. There was an existing functions-as-trees representation shared by the C and C++ front ends, and another used by the Java front end, but neither was adequate for use in optimization. In this paper, we will discuss the design of GENERIC, the new language-independent tree representation, and GIMPLE, the reduced subset used during optimization. | + | |
| - | + | ||
| - | ===An empirical comparison of ANSI-C to VHDL compilers:SPARK, ROCCC and DWARV=== | + | |
| - | ** Authors: Arcilio J. Virginia, Yana D. Yankova, Koen L.M. Bertels | + | |
| - | ** Year: 2007 | + | |
| - | ** File: [[Media:3_ANSIC_to_VHDL.pdf|download]] | + | |
| - | ** Description: | + | |
| - | + | ||
| - | ===Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths=== | + | |
| - | ** Authors: Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski | + | |
| - | ** Year: 2005 | + | |
| - | ** File: [[Media:Utilizing_horizontal_vertical_parallelism.pdf|download]] | + | |
| - | ** Description: An architecture that does not limit the number of custom functionalities that can be implemented on its datapath. Instead of using custom instructions and then relying on the decoder in hardware to generate the control signals, the control signal values are generated in compiler. | + | |
| - | + | ||
| - | ===FPGA-friendly Code Compression for Horizontal Microcoded Custom IPs=== | + | |
| - | ** Authors: Bita Gorjiara, Daniel Gajski | + | |
| - | ** Year: 2007 | + | |
| - | ** File: [[Media:FPGA_friendly_code_compression_for_horizontal.pdf|download]] | + | |
| - | ** Description: Reducing NISC (No-instruction Set Computer) code size by compression. | + | |
