State of The Art
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| - | ===Research Issues in Operating Systems for Reconfigurable Computing=== | + | [[Papers]] |
| - | * Authors: Grant B. Wigley and David A. Kearney | + | |
| - | * This paper appears in: In Proceedings of the International Conference on Engineering of Reconfigurable System and Algorithms(ERSA) | + | |
| - | * Year: 2002 | + | |
| - | * Abstract: As the number of system gates available on reconfigurable platforms increase beyond 20 million, the issue of the management of these resources and their sharing among may applications and users will become more of a concern. In this paper we describe the research issues for managing these resources in an operating system for a reconfigurable computer. We also detail a feasible set of components for the operating system and a feasible software architecture We show there is no current operating system implementation with these components. We propose a number of performance metrics which we believe are important measures of the quality of an operating system implementation. These include fragmentation of area, algorithm performance and application performance. We complete the paper with a status report on our implementation of an operating system for a reconfigurable computer. | + | |
| - | :[[Research Issues in Operating Systems for Reconfigurable Computing|Download]] | + | |
| - | ===ReConfigME: A Detailed Implementation of an Operating System for Reconfigurable Computing=== | + | [[Interesting Links]] |
| - | * Authors: Grant Wigley, David Kearney and Mark Jasiunas | + | |
| - | * This paper appears in: Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International Issue Date : 25-29 April 2006 On page(s): 8 pp. | + | |
| - | * ISBN: 1-4244-0054-6 | + | |
| - | * Year: 2006 | + | |
| - | * Abstract: Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. However, developing applications that share a device is difficult as the current design flow assumes the exclusive use of the FPGA resources. As a consequence, the designer must ensure that resources have been allocated for all possible combinations of loaded applications at design time. If the sequence of application loading and unloading is not known in advance, all resource allocation cannot be performed at design time because the availability of resources changes dynamically. In this paper, we present an implementation of an operating system that has the ability to share its FPGA resources dynamically among multiple executing applications. | + | |
| - | :[[Download_2|Research Issues in Operating Systems for Reconfigurable Computing]] | + | |
| - | * Operating Systems for FPGA Based Computers and Their Memory Management | + | [[Presentations]] |
| - | ** Authors: Klaus Danne | + | |
| - | ** Year: | + | |
| - | ** File: [[Media:OS_for_FPGA.pdf|download]] | + | |
| - | ** Description: Witam wszystkich, przesyłam dość ciekawy artykuł opisujący zadania systemu operacyjnego w dynamicznie rekonfigurowalnym FPGA (zarządzanie dostępem do pamięci, virtual adressing, dynamiczna alokacja itp). Chociaż zaprezentowane rozwiązania są bardzo ogólne, to uważam, że warto ten artykuł przeczytać. | + | |
| - | * An Adaptable Task Manager for Reconfigurable Architecture Kernels | + | [[Intermediate Representations]] |
| - | ** Authors: Yuriy Shiyanovskii, Francis Wolff, Chris Papachristou, Dan Weyer | + | |
| - | ** Year: 2009 | + | |
| - | ** File: [[Media:adaptable_task_manager.pdf|download]] | + | |
| - | ** Description: An operating system for a reconfigurable hardware fabric consisting of a distributed set of programmable processing tiles. Each tile is a small reconfigurable processor, having a set of registers, control unit and variable-width datapath. | + | |
| - | =VHDL= | + | [[HLL-to-VHDL Conversion Templates]] |
| - | * VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip | + | [[C2VHDL others]] |
| - | ** Authors: Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, Deming Chen | + | |
| - | ** Year: | + | |
| - | ** File: [[Media:Aspdac08-dc-invited.pdf|download]] | + | |
| - | ** Description: Zalaczony artykul przedstawia cos podobnego do tego, co chcemy zrealizowac, choc troche innego w koncepcji - application-specific multicores. | + | |
| - | + | ||
| - | * A Unified Hardware/Software Runtime Environment for FPGABased Reconfigurable Computers using BORPH | + | |
| - | ** Authors: Hayden KwokHay So, Artem Tkachenko and Robert Brodersen | + | |
| - | ** Year: 2006 | + | |
| - | ** File: [[Media:A_Unified_HardwareSoftware_Runtime_Environment_for_FPGA_using_BORPH_(2006).pdf|download]] | + | |
| - | ** Description: Podazajac tropem Piotrka natrafilem na ciakawy artykul (w zalaczniku) prezentujacy opracowany w Berkeley system operacyjny (rozszerzenie UINX'a) dla architektur opartych o FPGA. Artykul jest dosc "swiezy" bo z 2006 roku. Co wiecej, w Transactions on Embedded Computing Systems 2008 znalazlem artykul tych samych autorow, o tym samym tytule (niestety, nie udalo mi sie dotrzec do jego tresci). Zasadnicza czesc proponowanego systemu pracuje na procesorze PowerPC znajdujacym sie w glownym FPGA. Oprocz glownego FPGA sa jeszcze 4 uklady "user FPGA", w ktorych realizowane sa zadania uzytkownika. Osiagnieciem autorow jest ujednolicenie obslugi zadan implementowanych sprzetowo i programowo. Choc glowna koncepcja przedstawiona w artykule znacznie rozni sie od naszego pomyslu to warto go przeczytac ze wzgledu na prezentowane w nim mechanizmy komunikacji miedzy zadaniami i dostepu do pamieci. Lekture polecam szczegolnie naszym informatykom. Jak widac z artykulu, odpowiednia architektura sprzetu moze znacznie przyspieszyc prace systemu operacyjnego. Mocna strona artykulu jest to, ze nie przedstawia on jedynie luznych koncepcji ale konkretne, sprawdzone rozwiazania. | + | |
| - | + | ||
| - | * Generating the Communications Infrastructure for Module-based Dynamic Reconfiguration of FPGAs | + | |
| - | ** Authors: Shannon Koh | + | |
| - | ** Year: 2003 | + | |
| - | ** File: [[Media:Phdkoh.pdf|download]] | + | |
| - | ** Description: Po krotce mowiac, praca dotyczy opracowania narzedzi i metodologii (COMMA design flow opartej na Early Access Partial Reconfiguration Tool Flow) wspierajacych synteze ukladow wykorzystujacych modulowa rekonfiguracje dynamiczna na wspoczesne uklady rekonfigurowalne XILINX'a (rodzina Spartan-4) i jednoczesnie wspolpracujace z dostepnymi narzedziami producenta. Glowny nacisk w pracy polozony zostal na generacje i optymalizacje polaczen pomiedzy modulami dynamicznie rekonfigurowalnymi. Zaproponowane podejscie umozliwia zachowanie takich paramterow projektu jak np. ograniczenia czasowe, przy jednoczesnym spadku czasu dynamicznej rekonfiguracji do okolo 64% (w porownaniu do zastosowania dostepnych komercyjnie narzedzi). Autor w pracy implementuje model Brebnera ("fixed wiring harness" model), a tazke algorytm greedy'ego do łączenia grafow wsparte, rozwiniete czy tez nawet zastapione przez metode dynamicznego programowania. | + | |
| - | + | ||
| - | * The MOLEN Polymorphic Processor | + | |
| - | ** S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov, E. Moscu Panainte | + | |
| - | ** Year: 2006 | + | |
| - | ** File: [[Media:Molen.pdf|download]] | + | |
| - | ** Description: | + | |
| - | + | ||
| - | * Custom Processor Design Using NISC: A Case-Study on DCT algorithm | + | |
| - | ** Bita Gorjiara, Daniel Gajski | + | |
| - | ** Year: 2005 | + | |
| - | ** File: [[Media:Nisc.pdf|download]] | + | |
| - | ** Description: No-Instruction-Set-Computers (NISCs) that eliminate the instruction abstraction by compiling programs directly to a given datapath. | + | |
| - | + | ||
| - | =Compilers= | + | |
| - | + | ||
| - | * GENERIC and GIMPLE: A New Tree Representation for Entire Functions | + | |
| - | ** Authors: Jason Merrill | + | |
| - | ** Year: 2003 | + | |
| - | ** File: [[Media:GENERIC_and_GIMPLE.pdf|download]] | + | |
| - | ** Description: The tree SSA project requires a tree representation of functions for the optimizers to operate on. There was an existing functions-as-trees representation shared by the C and C++ front ends, and another used by the Java front end, but neither was adequate for use in optimization. In this paper, we will discuss the design of GENERIC, the new language-independent tree representation, and GIMPLE, the reduced subset used during optimization. | + | |
| - | + | ||
| - | * An empirical comparison of ANSI-C to VHDL compilers:SPARK, ROCCC and DWARV | + | |
| - | ** Authors: Arcilio J. Virginia, Yana D. Yankova, Koen L.M. Bertels | + | |
| - | ** Year: 2007 | + | |
| - | ** File: [[Media:3_ANSIC_to_VHDL.pdf|download]] | + | |
| - | ** Description: | + | |
| - | + | ||
| - | * Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths | + | |
| - | ** Authors: Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski | + | |
| - | ** Year: 2005 | + | |
| - | ** File: [[Media:Utilizing_horizontal_vertical_parallelism.pdf|download]] | + | |
| - | ** Description: An architecture that does not limit the number of custom functionalities that can be implemented on its datapath. Instead of using custom instructions and then relying on the decoder in hardware to generate the control signals, the control signal values are generated in compiler. | + | |
| - | + | ||
| - | * FPGA-friendly Code Compression for Horizontal Microcoded Custom IPs | + | |
| - | ** Authors: Bita Gorjiara, Daniel Gajski | + | |
| - | ** Year: 2007 | + | |
| - | ** File: [[Media:FPGA_friendly_code_compression_for_horizontal.pdf|download]] | + | |
| - | ** Description: Reducing NISC (No-instruction Set Computer) code size by compression. | + | |
