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| - | =HLL to VHDL Conversion Templates= | + | {| border="1" |
| - | {| border="1" | + | |style="background: #f9f9f9" align="center"|'''HLL Expression''' |
| - | |align="center"|'''HLL Expression''' | + | |style="background: #f9f9f9" align="center"|'''VHDL Expression''' |
| - | |align="center"|'''VHDL Expression''' | + | |style="background: #f9f9f9" align="center"|'''Remarks''' |
| - | |align="center"|'''Remarks''' | + | |
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| - | |align="center"|''variables representation'' | + | |style="background: #f9f9f9" align="center"|'''variables representation''' |
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| - | |''integer variable'' | + | |style="background: #f9f9f9" align="right"|''unsigned integer variable'' |
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| - | |floating point variable | + | |style="background: #f9f9f9" align="right"|''signed integer variable'' |
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| | + | |''generic'' (DATA_SIZE: natural := 32); |
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| | + | |''??'' |
| | + | |} |
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| | + | |style="background: #f9f9f9" align="right"|''floating point variable'' |
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| | + | {| |
| | + | |''generic'' (DATA_SIZE: natural := 32); |
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| | + | |''??'' |
| | + | |} |
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| | + | |style="background: #f9f9f9" align="center"|'''integer arithmetic operations''' |
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| | + | |style="background: #f9f9f9" align="center"|'''floating point arithmetic operations''' |
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| | |} | | |} |
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| | + | [[Media:Float_ug.pdf|floating point library specification]] |
Current revision
| HLL Expression
| VHDL Expression
| Remarks
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variables representation
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unsigned integer variable
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| generic (DATA_SIZE: natural := 32);
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signal : std_logic_vector (DATA_SIZE-1 downto 0);
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signed integer variable
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| generic (DATA_SIZE: natural := 32);
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??
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floating point variable
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| generic (DATA_SIZE: natural := 32);
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??
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integer arithmetic operations
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floating point arithmetic operations
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floating point library specification
