Polish National Science Centre project 2011/01/N/ST7/05242

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Call description

The project proposal was submitted for Polish National Science Centre call PRELUDIUM 1. This call type is addressed to young researchers who does not have a doctoral degree. The proposal must involve basic research.

Team members


Piotr Amrozik, PhD
phone: +48 (42) 631 27 22
e-mail: pamrozik@dmcs.pl
Detailed information

Role in the project: principal investigator.


Prof. Andrzej Napieralski
phone: +48 (42) 631 26 45
e-mail: napier@dmcs.pl
Detailed information

Role in the project: supervisor.

Proposal details

Project proposal entitled "Microarchitecture of computational elements for general purpose reconfigurable processor" was submitted to Polish National Science Centre on 14th of June 2011. It had been accepted and qualified for funding. The project started on 21st of December 2011 and ended on 20th of December 2013.

Project scientific goal

The main goal of the project is research on the modular dynamically reconfigurable microarchitectures due to their possible application in a general purpose microprocessor, which can break today’s paradigm of sequential thread execution in the fixed hardware resources.

The final result of the proposed project is aimed at extending the current knowledge on computer architecture hardware resources. To achieve this goal, besides the theoretical research on the new dynamically reconfigurable architecture of the general purpose processor, possibilities and constraints of its implementation in one of the up-to-date microelectronics technologies must be analysed as well.

Concept and plan of the research

The state of the art preview shows a great potential of dynamically reconfigurable devices to substitute, in near time, the nowadays processor architectures. Due to their specific features, it is not enough to propose only the novel architecture, which is expected to give better results in theory. There is a need of research on the solution which will be able to address known issues regarding dynamically reconfigurable devices, using a completely new approach to the current computing circuit implementation paradigms. Therefore, the realization of the project requires physical synthesis allowing designation of the actual capabilities of proposed circuit. Actually, proposed project constitutes joint research on fundamental computer architecture and on possibilities of utilizing it in a real device.

As it was mentioned earlier, within the confines of this project, the research on a possible usage of the modular multi-context dynamically reconfigurable microarchitecture as a general purpose microprocessor will be performed. During this research, the following aspects regarding the architecture will be considered:

  • dynamic reconfigurability of the circuit – this research will have direct impact on the flexibility and the speed of the circuit reconfiguration
  • multi-context reconfigurability with emphasis on data sharing between contexts – multi-context reconfiguration increases flexibility of usage of the resources and can help to decrease the number of required reconfigurations during a run-time
  • configuration memory – multi-context techniques implementation requires a large amount of resources for a configuration memory. Therefore, the full-custom design approach will be considered in order to reduce the occupied area
  • computing unit architectures – during this research multiple arithmetic architectures will be explored to check for those which can give advantageous realisation in proposed modular architecture
  • matrix granularity – it is important due to the usability of the device and has a direct impact on the size of required bitstreams and configuration method
  • internal connection interfaces – important due to the need of a flexible exploitation of hardware resources by tasks to be performed
  • memory interface – large number of parallel tasks will require well organized access to data from a memory what requires the research on a alternative solutions in respect to the ones in nowadays microprocessor architectures

The proposed architecture will be described in hardware description language VHDL and synthesized with one of the newest VLSI digital technologies. The verification of the theoretical assumptions will be performed through back-annotated post-layout simulations of proposed circuit.

Research methodology

Realisation of the project will be conducted in three steps:

  1. Architecture research and implementation: firstly, the author will search for possible circuit realisations and secondly the description of the proposed architecture will be prepared using VHDL hardware description language.
  2. Logic and physical synthesis of the device: this step will be based on the author’s current doctoral thesis which concerns the modular dynamically reconfigurable device design methodology.
  3. Verification: consists of evaluation of the basic features of the device: e.g. reasonable number of computing units (depends on chosen technology), reconfiguration speed, size of a bitstream, possible processing speed, etc. All this will be acquired by back-annotated post-layout simulations.


Main achievements of the project

  1. Development of general purpose processor architecture based on dynamically reconfigurable resources without employing fixed cores and their commonly used hardware like ALU or processor registers, and in particular:
    • development of flexible configuration method of CLB,
    • development of partition activation and deactivation mechanism,
    • development of matrix of CLB architecture supporting computations on 32/64-bit operands,
    • development of interface to access the partition to the memory.
  2. Realisation of the project resulted in two patent applications that were submitted to Polish Patent Office.
  3. Implementation of the developed processor in TSMC 65 nm technology process.
  4. The processor was roughly compared in terms of performance with other commercially available architectures and obtained result confirmed usability of the new architecture.

Realisation of the scientific goals - summary

All goals assumed in the project proposal were achieved. The details about the goals and they realisation is presented in table 1. During project realisation one additional goal had been realised, namely consistent and automated design environment dedicated to design of modular dynamically reconfigurable devices had been developed. This environment considerably speeded-up realisation of the reconfigurable processor architecture.

Table 1. Realisation of the assumed goals.
Assumed goals Realisation status
Research on a modular dynamically reconfigurable microarchitecture to determine whether it can be used as general purpose processor, in particular:
  • employing multi-context dynamical reconfiguration with special consideration of data exchange between context,
Achieved: development of dynamically reconfigurable matrix of CLB supporting multi-context data exchange and the mechanism of partition activation and deactivation (subject of patent).
  • development of computational elements architecture, selection of matrix granularity, development of internal connection interfaces,
Achieved: development of flexible CLB architecture supporting computations on 32/64-bit operands.
  • development of memory access interface,
Achieved: development of interface to access the partition to memory.
  • device implementation with one of the newest technology process,
Achieved: the device was implemented in TSMC 65 nm, automated implementation flow was developed.
  • realisation of post-layout simulations, and utilisation of obtained results to research on architecture and to comparison to typical processor architectures.
Achieved: post-layout simulations of the device confirming its correct operation was realised. Obtained results were used as a feedback to the research on the processor architecture and its comparison.
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