Polish National Science Centre project 2011/01/N/ST7/05242

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==Call description== ==Call description==
-The project proposal was submitted for Polish National Science Centre call PRELUDIUM [http://www.ncn.gov.pl/finansowanie-nauki/konkursy/typy/2?language=en]. This call type is addressed to young researchers which does not have a doctoral degree. The proposal must involve basic research.+The project proposal was submitted for Polish National Science Centre call [http://www.ncn.gov.pl/finansowanie-nauki/konkursy/typy/2?language=en PRELUDIUM 1]. This call type is addressed to young researchers who does not have a doctoral degree. The proposal must involve [http://www.ncn.gov.pl/sites/default/files/pliki/ustawy/ustawa-o-finansowaniu-nauki.pdf basic research].
==Team members== ==Team members==
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===Project scientific goal=== ===Project scientific goal===
<div class="center" style="width: auto; margin-left: auto; margin-right: auto;">''The main goal of the project is research on the modular dynamically reconfigurable microarchitectures due to their possible application in a general purpose microprocessor, which can break today’s paradigm of sequential thread execution in the fixed hardware resources.''</div> <div class="center" style="width: auto; margin-left: auto; margin-right: auto;">''The main goal of the project is research on the modular dynamically reconfigurable microarchitectures due to their possible application in a general purpose microprocessor, which can break today’s paradigm of sequential thread execution in the fixed hardware resources.''</div>
 +
 +The final result of the proposed project is aimed at extending the current knowledge on computer architecture hardware resources. To achieve this goal, besides the theoretical research on the new dynamically reconfigurable architecture of the general purpose processor, possibilities and constraints of its implementation in one of the up-to-date microelectronics technologies must be analysed as well.
===Concept and plan of the research=== ===Concept and plan of the research===
Line 33: Line 35:
===Research methodology=== ===Research methodology===
Realisation of the project will be conducted in three steps: Realisation of the project will be conducted in three steps:
-#Architecture research and implementation: firstly, the author will search for possible circuit realisations and secondly the description of the proposed architecture will be prepared using VHDL hardware description language+#Architecture research and implementation: firstly, the author will search for possible circuit realisations and secondly the description of the proposed architecture will be prepared using VHDL hardware description language.
-#Logic and physical synthesis of the device: this step will be based on the author’s current doctoral thesis which concerns the modular dynamically reconfigurable device design methodology+#Logic and physical synthesis of the device: this step will be based on the author’s current doctoral thesis which concerns the modular dynamically reconfigurable device design methodology.
#Verification: consists of evaluation of the basic features of the device: e.g. reasonable number of computing units (depends on chosen technology), reconfiguration speed, size of a bitstream, possible processing speed, etc. All this will be acquired by back-annotated post-layout simulations. #Verification: consists of evaluation of the basic features of the device: e.g. reasonable number of computing units (depends on chosen technology), reconfiguration speed, size of a bitstream, possible processing speed, etc. All this will be acquired by back-annotated post-layout simulations.
 +
 +==Results==
 +
 +===Main achievements of the project===
 +
 +# Development of general purpose processor architecture based on dynamically reconfigurable resources without employing fixed cores and their commonly used hardware like ALU or processor registers, and in particular:
 +#* development of flexible configuration method of CLB,
 +#* development of partition activation and deactivation mechanism,
 +#* development of matrix of CLB architecture supporting computations on 32/64-bit operands,
 +#* development of partition interface to memory access.
 +# In result of the project realisation two patent applications were submitted to Polish Patent Office.
 +# Implementation of the developed processor in [http://www.tsmc.com/english/dedicatedFoundry/technology/65nm.htm TSMC 65&nbsp;nm technology process].
 +# Performance of the developed processor was roughly compared to other architectures available on the market and obtained result confirmed usability of the new architecture.

Revision as of 09:11, 31 January 2014

Contents

Call description

The project proposal was submitted for Polish National Science Centre call PRELUDIUM 1. This call type is addressed to young researchers who does not have a doctoral degree. The proposal must involve basic research.

Team members

border Piotr Amrozik, PhD, phone: +48 (42) 631 27 22 e-mail: pamrozik@dmcs.pl Detailed information
Role in the project: principal investigator.


border Prof. Andrzej Napieralski, phone: +48 (42) 631 26 45 e-mail: napier@dmcs.pl Detailed information
Role in the project: supervisor.

Proposal details

Proposal was submitted on 14th of June 2011. It had been accepted and qualified for funding. The project started on 21st of December 2011 and ended on 20th of December 2013.

Project scientific goal

The main goal of the project is research on the modular dynamically reconfigurable microarchitectures due to their possible application in a general purpose microprocessor, which can break today’s paradigm of sequential thread execution in the fixed hardware resources.

The final result of the proposed project is aimed at extending the current knowledge on computer architecture hardware resources. To achieve this goal, besides the theoretical research on the new dynamically reconfigurable architecture of the general purpose processor, possibilities and constraints of its implementation in one of the up-to-date microelectronics technologies must be analysed as well.

Concept and plan of the research

The state of the art preview shows a great potential of dynamically reconfigurable devices to substitute, in near time, the nowadays processor architectures. Due to their specific features, it is not enough to propose only the novel architecture, which is expected to give better results in theory. There is a need of research on the solution which will be able to address known issues regarding dynamically reconfigurable devices, using a completely new approach to the current computing circuit implementation paradigms. Therefore, the realization of the project requires physical synthesis allowing designation of the actual capabilities of proposed circuit. Actually, proposed project constitutes joint research on fundamental computer architecture and on possibilities of utilizing it in a real device.

As it was mentioned earlier, within the confines of this project, the research on a possible usage of the modular multi-context dynamically reconfigurable microarchitecture as a general purpose microprocessor will be performed. During this research, the following aspects regarding the architecture will be considered:

  • dynamic reconfigurability of the circuit – this research will have direct impact on the flexibility and the speed of the circuit reconfiguration
  • multi-context reconfigurability with emphasis on data sharing between contexts – multi-context reconfiguration increases flexibility of usage of the resources and can help to decrease the number of required reconfigurations during a run-time
  • configuration memory – multi-context techniques implementation requires a large amount of resources for a configuration memory. Therefore, the full-custom design approach will be considered in order to reduce the occupied area
  • computing unit architectures – during this research multiple arithmetic architectures will be explored to check for those which can give advantageous realisation in proposed modular architecture
  • matrix granularity – it is important due to the usability of the device and has a direct impact on the size of required bitstreams and configuration method
  • internal connection interfaces – important due to the need of a flexible exploitation of hardware resources by tasks to be performed
  • memory interface – large number of parallel tasks will require well organized access to data from a memory what requires the research on a alternative solutions in respect to the ones in nowadays microprocessor architectures

The proposed architecture will be described in hardware description language VHDL and synthesized with one of the newest VLSI digital technologies. The verification of the theoretical assumptions will be performed through back-annotated post-layout simulations of proposed circuit.

Research methodology

Realisation of the project will be conducted in three steps:

  1. Architecture research and implementation: firstly, the author will search for possible circuit realisations and secondly the description of the proposed architecture will be prepared using VHDL hardware description language.
  2. Logic and physical synthesis of the device: this step will be based on the author’s current doctoral thesis which concerns the modular dynamically reconfigurable device design methodology.
  3. Verification: consists of evaluation of the basic features of the device: e.g. reasonable number of computing units (depends on chosen technology), reconfiguration speed, size of a bitstream, possible processing speed, etc. All this will be acquired by back-annotated post-layout simulations.

Results

Main achievements of the project

  1. Development of general purpose processor architecture based on dynamically reconfigurable resources without employing fixed cores and their commonly used hardware like ALU or processor registers, and in particular:
    • development of flexible configuration method of CLB,
    • development of partition activation and deactivation mechanism,
    • development of matrix of CLB architecture supporting computations on 32/64-bit operands,
    • development of partition interface to memory access.
  2. In result of the project realisation two patent applications were submitted to Polish Patent Office.
  3. Implementation of the developed processor in TSMC 65 nm technology process.
  4. Performance of the developed processor was roughly compared to other architectures available on the market and obtained result confirmed usability of the new architecture.
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