Polish-Swiss Research Programme team

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border Rafał Kiełbik, PhD, phone: +48 (42) 631 2722 e-mail: rkielbik@dmcs.pl Detailed information
Workpackages: Compilation, Dynamic Reconfiguration, Processor Architecture, Prototype, Final Chip


border Grzegorz Jabłoński, PhD, phone: +48 (42) 631 2648 e-mail: gwj@dmcs.p.lodz.pl Detailed information
Workpackages: Compilation, Dedicated Operating System, Dynamic Reconfiguration, Processor Architecture, Prototype, Final Chip


border Kamil Grabowski, PhD, phone: +48(42)631 2723 e-mail: kgrabowski@dmcs.p.lodz.pl Detailed information
Workpackages: Prototype, Final Chip


border Piotr Zając, PhD, phone: +48 (42) 631 2653 e-mail: pzajac@dmcs.p.lodz.pl Detailed information
Workpackage: Processor Architecture


border Bartłomiej Świercz, PhD, phone: +48 (42) 631 2723 e-mail: swierczu@dmcs.pl Detailed information
Workpackages: Compilation, Dedicated Operating System


border Bartosz Sakowicz, PhD, phone: +48 (42) 631 2721 e-mail: sakowicz@dmcs.pl Detailed information
Workpackage: Dedicated Operating System


border Adrian Romiński, PhD, phone: +48 (42) 631 2692 e-mail: rominski@dmcs.p.lodz.pl Detailed information
Workpackages: Prototype, Final Chip


border Dariusz Makowski, PhD, phone: +48 (42) 631 2720 e-mail: dmakow@dmcs.p.lodz.pl Detailed information
Workpackages: Dynamic Reconfiguration, Processor Architecture, Prototype, Final Chip


border Piotr Amrozik, MSc, phone: +48 (42) 631-27-22 e-mail: pamrozik@dmcs.pl Detailed information
Workpackages: Compilation, Dynamic Reconfiguration, Processor Architecture, Prototype, Final Chip


border Maciej Borzęcki, MSc, phone: e-mail: mborzecki@dmcs.pl Detailed information
Workpackages: Compilation, Dedicated Operating System


border Łukasz Kotynia, MSc, phone: e-mail: lkotynia@dmcs.p.lodz.pl Detailed information
Workpackages: Dynamic Reconfiguration, Processor Architecture, Prototype, Final Chip


border Adam Piotrowski, MSc, phone: +48 (42) 631 2720 e-mail: komam@dmcs.p.lodz.pl Detailed information
Workpackages: Compilation, Dedicated Operating System, Processor Architecture

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