Piotr Zaj?c, PhD

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PhD – in 2008 r. in Institut National des Sciences Appliquées, Toulouse, France, „Fault Tolerance through Self-configuration in the Future Nanoscale Multiprocessors”

Participation in Projects

Project „MasCotTe”(Maitrise et Controle des Temps d'Execution) financed by French Research Agency ANR (Agence Nationale de la Recherche), 01/07/2008 – 28/02/2009, Laboratoire d’Architecture et d’Analyse des Systemes du C.N.R.S, Toulouse, France, (title translation: Mastering and control of execution times).

Additional Courses and Trainings

LAAS-CNRS, Toulouse, France, 01/10/2006 – 28/02/2007 and 01/10/2007 – 28/02/2008. Scientific training in the frame of common PhD studies between Technical University of Lodz and Institut National des Sciences Appliquées of Toulouse.


P. ZAJĄC.: “Fault Tolerance through Self-configuration in Nanoscale Processors”, VDM Verlag, October 2009 r., ISBN 978-3-639-20274-8

Papers in international journals

J.H. COLLET, P. ZAJĄC, M. PSARAKIS, D. GIZOPOULOUS “Chip Self-Organization and Fault-Tolerance in Massively Defective Multicore Array”, IEEE Transactions on Dependable and Secure Computing, 04 Dec. 2009, ISSN: 1545-5971

Papers on international conferences

  1. J.H. COLLET, M. PSARAKIS, P. ZAJĄC, D. GIZOPOULOUS, A. NAPIERALSKI “Comparison of Fault-Tolerance Techniques for Massively Defective Fine- and Coarse-Grained Nanochips” 16th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), Łódź, 25-27 June 2009, ISBN 978-83-928756-0-4
  2. E. KOLONIS, M. NICOLAIDIS, D. GIZOPOULOUS, M. PSARAKIS, J.H. COLLET, P. ZAJĄC “Enhanced Self-Configurability and Yield in Multicore Grids” 15th IEEE International On-Line Testing Symposium, IOLTS 2009, Sesimbra-Lisbon, Portugal, June 24-27, 2009, ISBN: 978-1-4244-4596-7
  3. P. ZAJĄC, J. H. COLLET, A. NAPIERALSKI “Self-configuration and Reachability Metrics in Massively Defective Multiport Chips”, 14th IEEE International On-Line Testing Symposium, IOLTS 2008, Rhodes, Greece, 7-9 July 2008. ISBN:978-0-7695-3264-6
  4. P. ZAJĄC, J. H. COLLET "Production Yield and Self-Configuration in the Future Massively Defective Nanochips," 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems,. DFT '07, pp.197-205, 26-28 Sept. 2007, ISBN:0-7695-2885-6
  5. P. ZAJĄC, J.H. COLLET, J. ARLAT, Y. CROUZET “Resilience through Self-Configuration in Massively Defective NOCs”, Design, Automation and Test in Europe, DATE ’07, 16-20 April 2007, ISBN: 978-3-9810801-2-4
  6. P. ZAJĄC, J. H. COLLET, J. ARLAT, Y. CROUZET, “Resilience through Self-Configuration in Future Massively Defective Nanochips”, Supplemental Volume of the 37th Annual IEEE/IFIP Int. Conf. on Dependable Systems and Networks (DSN-2007) - Workshop on Dependable and Secure Nanocomputing, (Edinburgh, Scotland, UK), pp. 266-271, 2007, ISBN:0-7695-2855-4
  7. P. ZAJĄC, J. H. COLLET "Resilience, Production Yield and Self-Configuration in the Future Massively Defective Nanochips," 13th IEEE International On-Line Testing Symposium, IOLTS 07, pp.259-259, 8-11 July 2007, ISBN:0-7695-2918-6
  8. P. ZAJĄC, J. H. COLLET, Y. CROUZET, A. NAPIERALSKI "Contribution of communications to dependability in massively-defective general-purpose nanoarchitectures," 12th IEEE International On-Line Testing Symposium, IOLTS 2006, pp. 8, 10-12 July 2006, ISBN:0-7695-2620-9
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