HLL-to-VHDL Conversion Templates

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Revision as of 10:28, 20 January 2011
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-{| border="1"+{| border="1"
-|align="center"|'''HLL Expression'''+|style="background: #f9f9f9" align="center"|'''HLL Expression'''
-|align="center"|'''VHDL Expression'''+|style="background: #f9f9f9" align="center"|'''VHDL Expression'''
-|align="center"|'''Remarks'''+|style="background: #f9f9f9" align="center"|'''Remarks'''
|+ |+
-|align="center"|'''variables representation'''+|style="background: #f9f9f9" align="center"|'''variables representation'''
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-|align="right"|''unsigned integer variable''+|style="background: #f9f9f9" align="right"|''unsigned integer variable''
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{| {|
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-|align="right"|''signed integer variable''+|style="background: #f9f9f9" align="right"|''signed integer variable''
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{| {|
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-|align="right"|''floating point variable''+|style="background: #f9f9f9" align="right"|''floating point variable''
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{| {|
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-|align="center"|'''integer arithmetic operations'''+|style="background: #f9f9f9" align="center"|'''integer arithmetic operations'''
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|+ |+
-|align="center"|'''floating point arithmetic operations'''+|style="background: #f9f9f9" align="center"|'''floating point arithmetic operations'''
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|} |}

Revision as of 10:31, 20 January 2011

HLL Expression VHDL Expression Remarks
variables representation
unsigned integer variable
generic (DATA_SIZE: natural := 32);
signal : std_logic_vector (DATA_SIZE-1 downto 0);
signed integer variable
generic (DATA_SIZE: natural := 32);
??
floating point variable
generic (DATA_SIZE: natural := 32);
??
integer arithmetic operations
floating point arithmetic operations
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