?ukasz Kotynia, MSc

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MSc in Electronics and Telecommunications – awarded by Technical University of Lodz (Poland) in 2008, Thesis: “Design of CAM memories using FPGAs for implementing the encoder/decoder modules for PERLEXUS project”

Participation in Projects

  1. Project of VI FP EU: ” PERPLEXUS - Pervasive computing framework for modelling complex virtually-unbounded systems”, IST-2006-34632 (position: contractor).

Additional Courses and Trainings

  1. Internship at Cadence Design Systems (1 March 2009 – 28 February 2010) including among others:
    1. Advanced Synthesis with Encounter RTL Compiler
    2. Floorplanning, Physical Synthesis, Place and Route
    3. Basic Static Timing Analysis
    4. Signoff Timing Analysis with Encounter Timing System
  2. Cadence AMS Methodology Kit – Lodz, Poland, February 2009


  1. 2010 - One year internship at Cadence Design Systems competed with distinction
  2. 2008 – First position in best student ranking at Faculty of Electrical, Electronic, Computer and Control Engineering of Technical University of Lodz
  3. 2008 – First prize at the Cadence European Electronic Design Contest (announced during CDNLive! EMEA 2008 conference – Munich, Germany)

Papers on international conferences

  1. MORENO J. M., MADRENAS J., KOTYNIA L., “Synchronous Digital Implementation of the AER Communication Scheme for Emulating Large-Scale Spiking Neural Networks Models”, 2009 NASA/ESA Conference on Adaptive Hardware and Systems, San Francisco, California, USA, 2009, pp.189-196, ISBN: 978-0-7695-3714-6
  2. AMROZIK P., KOTYNIA L., MICHALIK P., JANKOWSKI M., NAPIERALSKI A., “Alternative design approach for signal switchboxes in nanometer process”, Proceedings of the 10th International Conference, CAD Systems in Microelectronics, CADSM 2009, Lviv-Polyana, Ukraine, 2009, pp. 60 – 64, ISBN: 978-966-2191-05-9
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