Grzegorz Jab?o?ski, PhD

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Contents

Diplomas

PhD – in 1999 on Technical University of Łódź, "Computer-aided design of electronic circuits with the application of distributed physical models of semiconductor devices"

Participation in Projects

International projects:

  1. 2009 - 2012 EUCard - Coordination for Accelerator Research and Development, FP7
  2. 2006 - 2010 PERPLEXUS - Pervasive computing framework for modelling complex virtually-unbounded systems, IST-2006-34632, FP6
  3. 2003 - 2009 CARE - Coordinated Accelerator Research in Europe RII3-CT-2003-506395, FP6
  4. 2002 – 2005 V EUROPEAN PROJECT IST-2000-30193 REASON - Research and Training Action for System on Chip Design, FP5
  5. 1995 – 1998 COPERNICUS 940922 – THERMINIC Thermal Investigation of Integrated Circuits
  6. 1994 – 1998 ESPRIT 8173 – BARMINT Basic Research for Microsystems Integration
  7. 1994 – 1996 TEMPUS JEN - 02031-93 Computer Aided Design and Engineering in Electronic Engineering Education
  8. 1992 – 1995 TEMPUS JEP – 4343 Education of computer aided design of modern VLSI circuits

National projects:

  1. 2006 - 2009 Metody i algorytmy projektowania układów FPGA tolerujących występowanie efektów SEU (Methods and algorithms for design of SEU-tolerant FPGA circuits)
  2. 1991 – 2001 Projektowanie układów scalonych Smart Power - metody i narzędzia specjalizowane do projektowania, realizacji i testowania (Design of Smart Power integrated circuits – methods and specialized tools for design, implementation and testing)
  3. 1997 – 1999 Komputerowa analiza układów elektronicznych z zastosowaniem wielowymiarowych modeli fizycznych przyrządów półprzewodnikowych mocy (Computer-aided design of electronic circuits with the application of distributed physical models of semiconductor devices) – Main researcher
  4. 1996 – 1998 Dwuwymiarowa symulacja komputerowa struktur unipolarno-bipolarnych mocy (Two-dimensional computer simulation of unipolar-bipolar power structures)

Commercial projects

  1. 2007-2008 Interface between CFDRC NanoTCAD and Cadence Spectre for CFDRC
  2. 2004 Design of a SOI integrated circuit for Tritem
  3. 2001 Interface between CFDRC Ace and Berkeley Spice for CFDRC

Additional Courses and Trainings

2004

  1. ANS’04: International Summer School on Selected Topics in Analog IC Design, Academy of Mining and Metallurgy, Kraków, Poland
  2. Course "High-Speed Analog Design for Optical Networking", Warsaw University of Technology, Poland
  3. Course “Practical aspects of digital IP cores design based on VHDL at behavioral and RT levels", Technical University of Łódź, Poland

2003

  1. Course “Silicon MEMS Technology”, Institute of Electron Technology, Poland
  2. Course “Techniques for Designing Testable ICs”, Tallinn Technical University, Estonia
  3. Course “Unified C++ based Design of Heterogeneous HW/SW Systems”, Katholieke Universiteit Leuven, Belgium

1997

VHDL Course, Slovak Technical University

1996

Industrial placement at the Technical Research Centre of Finland - VTT ELECTRONICS, Espoo

1995

Cadence IC Course, Slovak Technical University

Books

NAPIERALSKA M., JABŁOŃSKI G.: „Podstawy Mikroelektroniki”, KMiTI P.Ł. 2002 ISBN 83-89003-01-5. A.C.G.M. Lodart S.A., Łódź, ss.171

Book chapters

  1. NAPIERALSKI A., FURMAŃCZYK M., PACHOLIK J., JABŁOŃSKI G., WÓJCIAK W., NAPIERALSKA M., GRECKI M., CIOTA Z., Ali A. Ati, JANICKI M., ORLIKOWSKI M., ZUBERT M.: “The TULSOFT approach”, Book: "Basic research for microsystems integration", CEPADUES-EDITIONS, Toulouse, France, ISBN 2-85428-465-8, 1997, pp. 124-136.
  2. TUROWSKI M., JABŁOŃSKI G., NAPIERALSKI A.: “Case of Micromotor", Book: "Basic research for microsystems integration", CEPADUES-EDITIONS, Toulouse, France, ISBN 2-85428-465-8, 1997, pp. 143-149.
  3. SALMAN A.W., NAPIERALSKI A., TUROWSKI M., JABŁOŃSKI G.: "A New Approach for Finding Optimum Design of Electrostatic Micromotors", Kluwer Academic Publishers, Dordrecht/Boston/London, 1998, pp. 109-114.

Scripts

  1. NAPIERALSKA M., JABŁOŃSKI G., SICARD E.: “ Podstawy Mikroelektroniki – materiały pomocnicze do laboratorium dla kierunków studiów Elektronika i Informatyka”, Wyd. PŁ, LodArt, Łódź 2000, (ISBN 83-87202-59-2), ss.67
  2. MARAŃDA W., JABŁOŃSKI G., GRECKI M.: „Programowanie mikroprocesorów rodziny Motorola 680x0 w języku asemblera”. Materiały pomocnicze do laboratorium dla kierunków studiów Elektronika i Informatyka, Politechnika Łódzka, Łódź 2001, ss. 67 (ISBN 83-89003-20-1), 23 cm, (spons. TEMPUS SJEP 12216) – opiniodawca: prof.dr hab. inż. Andrzej Napieralski.

Papers in international journals

  1. MAKOWSKI D., MUKHERJEE B., SIMROCK S., JABŁOŃSKI G., NAPIERALSKI A., GRECKI M.: „Radiation monitoring system for X-FEL”, Measurement Science and Technology 18 No 8 (August 2007) pp. 2397-2403, ISSN 0957-0233
  2. Makowski Dariusz, Jabłoński Grzegorz, Grecki Mariusz, Mielczarek Jakub, Napieralski Andrzej, Simrock Stefan, Mukherjee Bhaskar: "Readout system for cost-effective radiation monitoring system" (No. TNS-00352-2006.R2) IEEE Transactions on Nuclear Science (TNS), vol., 54, No 4, August 2007, pp. 1178-1183, ISSN: 0018-9499
  3. PRZYGODA K., PIOTROWSKI A., JABŁOŃSKI G., MAKOWSKI D., POŹNIAK T., NAPIERALSKI A.: ”Prototype Control System for Compensation of Superconducting Cavities Detuning Using Piezoelectric Actuators”, pp. 2336-2340, IEEE Transactions on Nuclear Science Journal, Vol. 56, No 4, Part 3, August 2009, ISSN 0018-9499
  4. Makowski, D. ; Koprek, W. ; Jezynski, T. ; Piotrowski, A. ; Jablonski, G. ; Jalmuzna, W. ; Czuba, K. ; Predki, P. ; Simrock, S. ; Napieralski, A.: "Prototype Real-Time ATCA-Based LLRF Control System", IEEE Transactions on Nuclear Science Journal, Vol. 58, No 4, p. 1553-1561

Papers in national journals

  1. TUROWSKI M., JABŁOŃSKI G., NAPIERALSKI A., WIAK S.: “Computer-aided Analysis of Integrated Electrostatic Micromotors”, Biuletyn Polskiej Akademii Nauk, Vol.44, No.2, 1996, pp.177-184.
  2. ZIĘBA B., WOJCIECHOWSKI J., ZABIEROWSKI W., JABŁOŃSKI G., NAPIERALSKI A., ”Portal internetowy do symulacji przyrządów półprzewodnikowych z wykorzystaniem technologii CORBA” ELEKTRONIKA 11/2004, ss. 12-15, ISSN 0033-2089
  3. S.Bek, T.Poźniak, Ł.Starzak, G.Jabłoński: „Zagadnienia filtracji harmonicznych w układach aktywnej korekcji współczynnika mocy”, Zeszyty Naukowe „Elektryka” nr 103, str. 155-164, Wydawnictwo Politechniki Łódzkiej, s. 224, B5, ISSN: 0374-4817
  4. Adam Piotrowski, Mariusz Orlikowski, Tomasz Kozak, Paweł Prędki, Grzegorz Jabłoński, Dariusz Makowski, Andrzej Napieralski: "Software optimisation in high efficiency data acquisition systems", ELEKTRONIKA - KONSTRUKCJE, TECHNOLOGIE, ZASTOSOWANIA 12/2011. ss. 68-72, ISSN 0033-2089

Papers on international conferences

  1. NAPIERALSKI A., PACHOLIK J., GRECKI M., FURMAŃCZYK M., JABŁOŃSKI G., TUROWSKI M., NAPIERALSKA M. CIOTA Z., WIĘCEK B.: Thermal design of silicon micropump. Third WORKSHOP in the Frame of ESPRIT Project (European Strategic Program for Research and Development in Information Technology - CEC-Contract No 8173 - BARMINT (Basic Research for Microsystems Integration)) , 2 December 1994, Barcelona, Spain..
  2. TUROWSKI M., JABŁOŃSKI G., NAPIERALSKI A, Sławomir WIAK: "Electromechanical and Thermal Modelling of IC-processed Micromotors", 2nd Int. Workshop: "MIXED DESIGN OF VLSI CIRCUITS -EDUCATION OF COMPUTER AIDED DESIGN OF MODERN VLSI CIRCUITS ", Kraków, POLAND, 29-31 May 1995, pp. 343-348.
  3. PACHOLIK J., FURMAŃCZYK M., JABŁOŃSKI G., TUROWSKI M., GRECKI M., NAPIERALSKI A.:(Lodz, PL), "Thermomechanical Design of Silicon Micropump", IInd Workshop: "MIXED DESIGN OF VLSI CIRCUITS -EDUCATION OF COMPUTER AIDED DESIGN OF MODERN VLSI CIRCUITS "Within the framework of the TEMPUS JEP 4343, Kraków, POLAND, 29-31 May 1995, pp.373-378.
  4. TUROWSKI M., WIAK S., JABŁOŃSKI G., NAPIERALSKI A., BARBA P.DI., SAVINI A., KRAWCZYK A.: "Silicon Micromotors - Problems of Numerical Modeling", Polish-Japanese Joint Seminar on Electromagnetic Field Computations, Oita, Japan, 8-11 June 1995.
  5. NAPIERALSKI A., JABŁOŃSKI G.: “Pyrtherm for Windows - User Friendly Thermal CAD Software”, International Workshop on Thermal investigations of ICs and Microstructures, THERMINIC, Grenoble 25-26/09/1995 , pp.32-37.
  6. FURMAŃCZYK M., JABŁOŃSKI G., NAPIERALSKI A., PACHOLIK J.: “The 3D Transient Thermal Simulation With Arbitary Border Condition”, International Workshop on Thermal investigations of ICs and Microstructures, THERMINIC, Grenoble 25-26/09/1995 , pp.70-75.
  7. FURMAŃCZYK M., JABŁOŃSKI G., NAPIERALSKI A.: “Comparison of two thermal simulation programs MONSTR and TULSOFT”, 4th WORKSHOP in the Frame of ESPRIT Project (European Strategic Program for Research and Development in Information Technology) - CEC-Contract No 8173 -BARMINT (Basic Research for Microsystems Integration), 14-15 December 1995, Bellaterra-Barcelona, Spain).
  8. JABŁOŃSKI G., POWIERZA J., JANICKI M., NAPIERALSKI A.: „Measurements of thermal resistance of an IC”, BARMINT Internal Report, Fourth WORKSHOP, Bellaterra-Barcelona, Spain, December 1995
  9. Grzegorz JABŁOŃSKI, E. De BAETSELIER, Marek TUROWSKI, Tomasz POŹNIAK, Andrzej NAPIERALSKI: ”Power Control ASIC for Hybrid Circuit Application”, Proceedings of the 3rd Advanced Training Course: „Education of computer aided design of modern ICs and devices”, MIXDES’96, Technical University of Łódź, Poland, 30 May - 1 June 1996, pp.507-512.
  10. FURMAŃCZYK M., JABŁOŃSKI G.,NAPIERALSKI A.: „Thermal simulation with TULSOFT package in the CADENCE design framework”, THERMINIC International Workshop on Thermal investigations of ICs and Microstructures, September 25-27, 1996, Budapest, Hungary, pp 35-40.
  11. Mariusz GRECKI, Grzegorz JABŁOŃSKI, Marcin JANICKI, Andrzej NAPIERALSKI: „Thermal Measurements of Integrated Circuits and Microsystems with Application of Computer-Based Thermography”, BARMINT Internal Report ,Fifth WORKSHOP, May 1996, Toulouse, France.
  12. Grzegorz JABŁOŃSKI, E. De BAETSELIER, Marek TUROWSKI, Tomasz POŹNIAK, Andrzej NAPIERALSKI: ”Power Control ASIC for Hybrid Circuit Application”, Proceedings of the 3rd Advanced Training Course: „Education of computer aided design of modern ICs and devices”, MIXDES’96, Technical University of Łódź, Poland, 30 May - 1 June 1996, pp.507-512.
  13. FURMAŃCZYK M., JABŁOŃSKI G.,NAPIERALSKI A.: „Thermal simulation with TULSOFT package in the CADENCE design framework”, THERMINIC International Workshop on Thermal investigations of ICs and Microstructures, September 25-27, 1996, Budapest, Hungary, pp 35-40.
  14. Grzegorz JABŁOŃSKI, Tomasz POŹNIAK, Wojciech WÓJCIAK, Andrzej NAPIERALSKI: “Thermal Benchmark Integrated Circuit in BiCMOS Technology”, THERMINIC’97, 3rd International Workshop on Thermal investigations of ICs and Microstructures, September 21-23, 1997, Cannes “Côte d’Azur”, France, pp. 34-36.
  15. Grzegorz JABŁOŃSKI, Tomasz POŹNIAK, Wojciech WÓJCIAK, Andrzej NAPIERALSKI: “Integrated Circuit for Thermal Measurement in BiCMOS Technology”, MIXDES’97, 4th International Workshop Mixed Design of Integrated Circuits and Systems, Poznañ, Poland, 12-14 June 1997, pp.265-270.
  16. Abdul W.SALMAN, Andrzej NAPIERALSKI, Marek TUROWSKI, Grzegorz JABŁOŃSKI: “New Approach and Some Considerations for Finding The Optimum Design of Electrostatic Micromotor”, MIXDES’97, 4th International Workshop Mixed Design of Integrated Circuits and Systems, Poznañ, Poland, 12-14 June 1997, pp.503-510
  17. Grzegorz JABŁOŃSKI, Mariusz GRECKI, Marek TUROWSKI: “Two-Dimensional Simulation in Semiconductor Devices Teaching”, MIXDES’97, 4th International Workshop Mixed Design of Integrated Circuits and Systems, Poznañ, Poland, 12-14 June 1997, pp.765-770.
  18. Mariusz GRECKI, Grzegorz JABŁOŃSKI, Andrzej NAPIERALSKI: "MOPS - Parallel environment for Simulation of Electronic Circuits Using Physical Models of Semiconductor Devices", 4th European PVM/MPI Users' Group Meeting, November 3-5, 1997, Kraków, Poland, pp.478-485
  19. SALMAN A.W., NAPIERALSKI A., JABŁOŃSKI G.: “An optimization scheme of micromotor design based on modified parallel plate model”, Proceedings of 5th International Conference: „Mixed Design of Integrated Circuits and Systems”, MIXDES’98, Łódź, Poland, 18-20 June 1998, pp.387-390
  20. JABŁOŃSKI G., NAPIERALSKA M.: “Micromachined Electro-Thermal Converter: Measurements and Parameter Extraction”, THERMINIC’98, 4th International Workshop on Thermal investigations of ICs and Microstructures, September 27-29, 1998, Cannes“Cote d,Azur”, France, pp.69-72
  21. GRECKI M., JABŁOŃSKI G., NAPIERALSKI A.: “Transient Temperature Evaluation During Switching Process in IGBT Transistor”; 4th International Seminar on Power Semiconductors ISPS'98, 2-4 September 1998, pp.119-124, Praga, Czechy
  22. GRECKI M., JABŁOŃSKI G.: “Two-Dimensional Model of SITh”; 4th International Seminar on Power Semiconductors ISPS'98, 2-4 September 1998, pp239-244, Praga, Czechy
  23. SALMAN A.W., NAPIERALSKI A., JABŁOŃSKI G.: „Simulation and Optymization of Variable Capacitance (VC) Micromotors, Using Modified Parallel-Plate Model”, MSM'99, International Conference on Modeling and Simulation of Mikrosystems, April 19-21, 1999, San Juan, Puerto Rico, USA, pp.609-612, 27 cm
  24. JANICKI M., POŹNIAK T., TYLMAN W., JABŁOŃSKI G., NAPIERALSKI A.: “Infrared Measurements of A Thermal Test Integrated Circuit”, International Conference on Modern Problems of Telecommunications, Computer Science and Engineers Training TCSET’2000, 14-19 February 2000, Lviv-Slavsko,Ukraine, pp.202-203.
  25. SALMAN A., NAPIERALSKI A., JABŁOŃSKI G.: “A New Analytical Micromotor Design Models for CAD PC-Design Tools”, MSM'2000, International Conference on Modeling and Simulation of Microsystems, March 27-29, 2000, San Diego, CA, USA, pp.692-695.
  26. JANICKI M., TYLMAN W., POŹNIAK T., JABŁOŃSKI G., NAPIERALSKI A.: “Measurement and Simulation of A Thermal Test Integrated Circuit”, In Proceeding 7th International Workshop Conference: " Mixed Design of Integrated Circuit and Systems", MIXDES'2000, Gdynia, Poland, 15-17 June 2000, pp. 347-350, A4.
  27. KIEŁBIK R., MORENO J.M., NAPIERALSKI A., JABŁOŃSKI G., SZYMAŃSKI T.: „High-Level Partitioning of Digital Systems Based on Reconfigurable Devices”, 12th International Conference, FLP 2002, Montpellier, France, September 2-4, pp.271-280, (Springer) (IST – 2001-34016-RECONF2)
  28. GRECKI M., JABŁOŃSKI G., WYSOCKI T.: „Application of Parallel Proce4ssing to the Simulation of Semiconductor Devices”, ISPS’02 – 6th International Seminar on Power Semiconductors, Praque, 4-6 September 2002, pp.167-172
  29. SZANIAWSKI K., PODSIADŁY P.P., JABŁOŃSKI G.: „A Methodology of Developing Reduced Linear Mechanical Models for MEMS Microstructures”, Proceedings of the 9th International Conference “Mixed Design of Integrated Circuits and Systems” MIXDES’2002, Wrocław, Poland 20-22 June 2002, pp. 407-412
  30. NAPIERALSKI A., JANICKI A., JABŁOŃSKI G., :„ Teaching System-on-Chip Design at Technical University of Lodz”, International Conference “The Experience of Designing and Application of CAD Systems in Microelectronics” CADSM 2003 Lviv Polytechnic National University, February 18-22, 2003, Lviv-Slavsk, Ukraine, pp. 30-39, ISBN 966-553-278-2
  31. ZIĘBA B., WOJCIECHOWSKI J., JABŁOŃSKI G., ZABIEROWSKI W., NAPIERALSKI A., :Web-Based Distributed Physic-Based Simulation System of Semiconductor Diode Structure” 10th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2003, 26-28 June 2003, Łódź, Poland , pp. 690-693, ISBN 83-7283-095-9
  32. JABŁOŃSKI G., MARAŃDA W., MAKOWSKI D.,”PV Data Acquisition System with Web Interface,” 19th European PV Solar Energy Conference, Paris, June 2004, pp 2918-2919, ISBN 88-89407-02-6
  33. MAKOWSKI D., JABŁOŃSKI G., MARAŃDA W., ”Online I–V Characteristics Monitoring for 1kWp PV Generator”,19th European PV Solar Energy Conference, Paris, June 2004,pp.2511-2513 , ISBN 88-89407-02-6
  34. MARAŃDA W., JABŁOŃSKI G., MAKOWSKI D.,”1kWp PV System at Technical University of Lodz in Poland”,19th European PV Solar Energy Conference, Paris, June 2004,pp.2915-2917 ISBN 88-89407-02-6
  35. MAKOWSKI D., GRECKI M., JABŁOŃSKI G. “Application of A Genetic Algorithm to Design of Radiation Tolerant Programmable Devices” 11th International Conference MIXDES 2004, Szczecin , Poland 24-26 June, pp. 463-467, ISBN 83-919289-7-7
  36. MAKOWSKI D., MARAŃDA W., JABŁOŃSKI G. “Online Photovoltaic I-V Characteristics Monitoring System at Technical University of Lodz” 11th International Conference MIXDES 2004, Szczecin , Poland 24-26 June, pp. 523-526, ISBN 83-919289-7-7
  37. S. Bek, Ł. Starzak, D. Makowski, and G. Jabłoński, “Measurements of 500 W Power Factor Correction Boost Converter,” CADSM, Lviv-Polyana, Ukraine, February 23–26, 2005 pp.90-98, ISBN 966-553-431-9
  38. G. JABLONSKI, K. SZANIAWSKI, M. JANKOWSKI „An Educational Circuit for Measuring Logic Gate Propagation Delays” 12 th International Conference MIXDES 2005, Kraków, Poland, 23-25 June, pp. 829 - 834, vol. 2, ISBN 83-919289-9-3
  39. Makowski D., Jabłoński G., Grecki M., Mielczarek J., Napieralski A.: „FPGA-based Neutron Radiation Tolerant Microcontroller”, Technical Proceedings of The Nanotechnology Conference and Trade Show, NSTI Nanotech, Boston, Massachusetts, USA, 7-11 maja 2006, wyd. Nano Science and Technology Institute, Publishing Office, Cambridge MA, USA, ISBN 0-9767985-8-1 + CD-ROM vol.1-3: ISBN: 0-9767985-9-X, str. 90-93, vol. 3, str. 892, A4.
  40. Janicki M., Makowski D., Kędziora P., Starzak Ł., Jabłoński G., Bek S.: „Improvement of PFC Boost Converter Energy Performance Using Silicon Carbide Diode”, 13th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2006, 22-24 czerwca 2006, Gdynia, wyd. KMiTI, str. 615-618, ISBN 83-922632-9-1, str. 808, A4.
  41. Malinowski Paweł, Makowski Dariusz, Jablonski Grzegorz, Napieralski Andrzej: "DESIGN OF RADIATION TOLERANT READOUT SYSTEM FOR AN INTEGRATED SRAM BASED NEUTRON DETECTOR", NSTI-NanoTech 2007, Vol.3, pp. 248-251, 20-24 Maj 2007, ISBN 1420061844.
  42. E.Piwowarska, W.Kuźmicz, G.Farkas, A.Poppe, M.Hristov, E.Manolov, B.Weber, J.Butas, G.Jabłoński, A.Jarosz, A.Kos, A.Golda, R.Długosz: “AnaDig – an Educational Chip for VLSI Device Characterization”, IEEE International Conference on Microelectronic Systems Education (MSE’07) 3-4 June 2007 San Diego, California, IEEE Computer Society, pp.19-20, 0-7695-2849-X/07. ISBN 4231629.
  43. Adam Piotrowski, Szymon Tarnowski, Grzegorz Jabłoński, Andrzej Napieralski, “Integral Interface - Universal Communication Interface for FPGA-based Projects”, 14th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2007, 21-23 czerwca 2007, Ciechocinek, wyd. KMiTI, str. 115-119, ISBN 83-922632-4-3, str. 713, A4.
  44. Grzegorz Jabłoński, Konrad Przygoda, “Low-latency Implementation of Coordinate Conversion in Virtex II Pro FPGA”, 14th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2007, 21-23 czerwca 2007, Ciechocinek, wyd. KMiTI, str. 120-123, ISBN 83-922632-4-3, str. 713, A4.
  45. Marek Turowski, Ashok Raman, Grzegorz Jabłoński, “Mixed-mode Simulation and Analysis of Digital Single Event Transients in Fast CMOS Ics”, 14th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2007, 21-23 czerwca 2007, Ciechocinek, wyd. KMiTI, str. 433-438, ISBN 83-922632-4-3, str. 713, A4.
  46. M. Wojtczak, D. Makowski, Jabłoński G, M. Grecki, and S. Simrock, “DSP-based system for advanced radiation tolerant algorithms evaluation”, Proceedings of SPIE Vol. 6159, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments IV, pp. 139–146, 2005, ISBN 0-8194-6211-4
  47. W.Dębowski, K.Przygoda, G.Jabłoński A.Napieralski, B.Mukherjee : “A Novel Approach for Real Time Neutron Radiation Monitoring Based on the Bubble Dosimeter”, 15th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2008, 19-21 czerwca 2008, Poznań, Poland, wyd. KMiTI, str. 93-96, ISBN 83-922632-7-8, str. 639, A4.
  48. A.Piotrowski, D.Makowski, G.Jabłoński, S.Tarnowski, A.Napieralski: “Hardware Fault Tolerance Implemented in Software at the Compiler Level with Special Emphasis”, 15th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2008, 19-21 czerwca 2008, Poznań, Poland, wyd. KMiTI, str. 115-120, ISBN 83-922632-7-8, str. 639, A4.
  49. Simrock, S.; Butkowski, L.; Grecki, M.; Jezynski, T.; Koprek, W.; Jablonski, G.; Jalmuzna, W.; Makowski, D.; Piotrowski, A.; Czuba, K.:”Evaluation of an ATCA based LLRF system at FLASH”, Mixed Design of Integrated Circuits & Systems, 2009., Page(s): 111 – 114
  50. T. Kucharski, A. Piotrowski, D. Makowski, G. Jabłoński, “PCI Express Communication Layer for ATCA-based Linear Accelerator Control System”, Mixed Design of Integrated Circuits & Systems, 2009
  51. S. Szachowałow, D. Makowski, G. Jabłoński, A. Napieralski, Ł. Butkowski, W. Koprek, S. Simrock, “Software for Data Acquisition AMC Module with PCI Express Interface” , Mixed Design of Integrated Circuits & Systems, 2009
  52. Grecki, M.; Jablonski, G.; Makowski, D.; “Improvements of SEU tolerance by spatial redundancy in digital circuits”, , Mixed Design of Integrated Circuits & Systems, 2009

Papers on national conferences

  1. TUROWSKI M., JABŁOŃSKI G., NAPIERALSKI A., WIAK S.: “Computer Aided Analysis of Integrated Electrostatic Micromotors” XVIII KKTOiUE 1995, Polana Zgorzelisko, 25-27 październik 1995, ss. 299-304.
  2. Mariusz GRECKI, Grzegorz JABŁOŃSKI, Marek TUROWSKI, Andrzej NAPIERALSKI: “Two-Dimensional Simulation of Turn-off Process in IGBT”, XXth, KKTOiUE’97, Kołobrzeg, 21-24.10.1997, pp.289-294.
  3. WÓJCIAK W., JABŁOŃSKI G., NAPIERALSKA M., MARAŃDA W., NAPIERALSKI A.: “Elektro-Thermal Converter in CMOS Technology-Modeling, Simulation and Design Aspects”, XXI KKTOiUE, Kiekrz, 22-24 październik 1998, ss.357-362
  4. GRECKI M., JABŁOŃSKI G., DĄBROWSKI M.: „Transmission and Reception of Multifrequency R-2 Signals Based on DSP Processors”, XXII KKTOiUE, Proceedings of the XXIInd National Konference on Circuit Theory and Electronic Networks, Warszawa – Stare Jabłonki, october 20-23, 1999, vol. 2/2, pp.509-514, (ISBN 83-909-593-0-5), 24 cm.
  5. POŹNIAK T., NAPIERALSKI A., JABŁOŃSKI G., ZARASKA W., CIEŻ M., GANDURSKA J.: “Możliwości realizacji układów Smart Power w warunkach krajowych”, VII Konferencja Naukowa “Technologia Elektronowa” ELTE 2000, Polanica Zdrój, 18-22 września 2000, MN38, A4; ss.504-509,
  6. KIEŁBIK R., NAPIERALSKI A., JABŁOŃSKI G., SZYMAŃSKI T., MORENO J.M.: „Algorytm dzielenia struktury opisanej w języku VHDL na dwie równoważne jej podstruktury”, V Krajowa Konferencja Naukowa RUC'2002 nt.: Reprogramowalne Układy Cyfrowe, Szczecin 9-10 maja 2002r. ss.51-58. A5,
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