User contributions
From REuP Project
(Latest | Earliest) View (previous 50) (next 50) (20 | 50 | 100 | 250 | 500).
- 10:28, 15 July 2010 (hist) (diff) Papers (→Adapting and automating XILINX's partial reconfiguration flow for multiple module implementations)
- 10:24, 15 July 2010 (hist) (diff) Restricted page (top)
- 10:23, 15 July 2010 (hist) (diff) Image:Adapting and Automating XILINXs Partial Reconfiguration Flow for Multiple Module Implementations (2007).pdf (top)
- 10:23, 15 July 2010 (hist) (diff) Papers (→Adapting and automating XILINX's partial reconfiguration flow for multiple module implementations)
- 10:22, 15 July 2010 (hist) (diff) Papers (→Borph: an operating system for fpga-based reconfigurable computers)
- 09:24, 15 July 2010 (hist) (diff) Restricted page (top)
- 09:23, 15 July 2010 (hist) (diff) Image:An Operating System for FPGA-Based Reconf Comp (2007).pdf (top)
- 09:23, 15 July 2010 (hist) (diff) Papers (→Borph: an operating system for fpga-based reconfigurable computers)
- 09:22, 15 July 2010 (hist) (diff) Papers (→Task scheduling for heterogeneous reconfigurable computers)
- 09:20, 15 July 2010 (hist) (diff) Restricted page (top)
- 09:19, 15 July 2010 (hist) (diff) Image:Task Scheduling for Heterogeneous Computers (2004).pdf (top)
- 09:18, 15 July 2010 (hist) (diff) Papers (→Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations)
- 09:16, 15 July 2010 (hist) (diff) Restricted page (top)
- 09:15, 15 July 2010 (hist) (diff) Image:Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures (2009).pdf (top)
- 09:15, 15 July 2010 (hist) (diff) Papers (→Asynchronous PipeRench: architecture and performance evaluations)
- 09:13, 15 July 2010 (hist) (diff) Papers (→PipeRench: A virtualized programmable datapath in 0.18 micron technology)
- 09:13, 15 July 2010 (hist) (diff) Papers (→Asynchronous PipeRench: architecture and performance evaluations)
- 09:12, 15 July 2010 (hist) (diff) Restricted page (top)
- 09:11, 15 July 2010 (hist) (diff) Image:Asynchronous PipeRench Architecture and Performance Estimations (2003).pdf (top)
- 09:11, 15 July 2010 (hist) (diff) Papers (→PipeRench: A virtualized programmable datapath in 0.18 micron technology)
- 09:08, 15 July 2010 (hist) (diff) Restricted page (top)
- 09:07, 15 July 2010 (hist) (diff) Image:PipeRench - Virtualized Programmable Datapath (2002).pdf (top)
- 09:07, 15 July 2010 (hist) (diff) Papers (→A Unified HW/SW Operating System for Partially Runtime Reconfigurable FPGA based Computer Systems)
- 09:05, 15 July 2010 (hist) (diff) Papers (→A Unified HW/SW Operating System for Partially Runtime Reconfigurable FPGA based Computer Systems)
- 09:04, 15 July 2010 (hist) (diff) Restricted page (top)
- 09:04, 15 July 2010 (hist) (diff) Restricted page
- 09:02, 15 July 2010 (hist) (diff) Image:A Unified HWSW Operating System for Partially Runtime Reconfigurable FPGA (2008).pdf (top)
- 09:02, 15 July 2010 (hist) (diff) Papers (→Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs)
- 08:56, 15 July 2010 (hist) (diff) Restricted page (top)
- 08:55, 15 July 2010 (hist) (diff) Image:Enhanced Architectures, Design Methodologies And Cad Tools For DR of Xilinx FPGAs (2006).pdf (top)
- 08:55, 15 July 2010 (hist) (diff) Papers (→VHDL Modeling of Fast Dynamic Reconfiguration on Novel Multicontext RAM-based Field Programmable Devices)
- 08:53, 15 July 2010 (hist) (diff) Restricted page (top)
- 08:53, 15 July 2010 (hist) (diff) Image:FIPSOC - VHDL Modeling of Fast Dynamic Reconfiguration (1997).pdf (top)
- 08:52, 15 July 2010 (hist) (diff) Papers (→Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor)
- 08:49, 15 July 2010 (hist) (diff) Restricted page (top)
- 08:48, 15 July 2010 (hist) (diff) Image:Application Acceleration with the Explicitly Parallel Operations System (2008).pdf (top)
- 08:47, 15 July 2010 (hist) (diff) Papers (→The Design and Implementation of Hardware Task Configuration Management Unit on Dynamically Reconfigurable SoC)
- 08:45, 15 July 2010 (hist) (diff) Restricted page (top)
- 08:45, 15 July 2010 (hist) (diff) Image:The Design and Implementation of Hardware Task Configuration Management Unit on DR SoC (2009).pdf (top)
- 08:44, 15 July 2010 (hist) (diff) Papers (→A Hardware Resource Management System for Adaptive Computing on Dynamically Reconfigurable Devices)
- 08:41, 15 July 2010 (hist) (diff) Restricted page (top)
- 08:40, 15 July 2010 (hist) (diff) Papers (→Hardware Supported Task Scheduling on Dynamically Reconfigurable SoC Architectures)
- 08:38, 15 July 2010 (hist) (diff) Restricted page (top)
- 08:38, 15 July 2010 (hist) (diff) Image:Hardware Supported Task Scheduling on Dynamically Reconfigurable SoC Architectures (2008).pdf (top)
- 08:37, 15 July 2010 (hist) (diff) Restricted page
- 08:36, 15 July 2010 (hist) (diff) Image:Hardware Resource Management System for Adaptive Computing (2006).pdf (top)
- 08:35, 15 July 2010 (hist) (diff) Papers (→Incremental reconfiguration for pipelined applications)
- 08:33, 15 July 2010 (hist) (diff) Restricted page (top)
- 08:31, 15 July 2010 (hist) (diff) Image:Incremental Reconfiguration for Pipelined Applications (1997).pdf (top)
- 08:31, 15 July 2010 (hist) (diff) Papers (→Multitasking on FPGA Coprocessors)
(Latest | Earliest) View (previous 50) (next 50) (20 | 50 | 100 | 250 | 500).