REuP Project - New pages [en]

UE 7FP ICT FET Open project

Pamrozik — Mon, 03 Feb 2014 16:21:31 GMT

Summary:

==General call information==
It was [http://cordis.europa.eu/fp7/dc/index.cfm?fuseaction=usersite.FP7DetailsCallPage&call_id=319 ICT FET Open Call in frame of the United Europe 7th Framework Progarmme]. Targeted type of funding scheme: small or medium-scale focused research project (STREP).

Proposal must be strictly anonymous, which means that there must be neither name of the organisations involved in the consortium nor any other information that could identify the applicants. Furthermore, strictly no bibliographic references are allowed in the proposal.

==Proposal general information==
===Project name for the call===
Reconfigurable General-Purpose Processor (RGPP)

===Abstarct of the proposal===
This project introduces an innovative, completely novel approach to architecture of general purpose processor. The concept exploits the parallelism of data processing and resource reuse of dynamically reconfigurable FPGAs (Field Programmable Gate Arrays), without any impact on development of new applications as well as migration (porting) of the existing ones. The proposed solution is an FPGA-based implementation of an instructionless, general-purpose processor, where there are no sequentially executed instructions but all tasks are implemented in the reconfigurable hardware. The process of translating individual tasks (instructions) into hardware representation is done in a completely automatic way. The whole array of reconfigurable blocks can be modified at runtime using a small fixed reconfiguration management unit.
The feasibility of the proposed unique hardware architecture will be confirmed with an Application Specific Integrated Circuit (ASIC). Furthermore, the tools for compilation, application execution and a dedicated operating system will be elaborated in the project. Achieved results, if successful, will constitute a breakthrough in the domain of computer architecture. The accomplished solution will open new horizons for software developers, being at the same time fully backward compatible as far as existing applications and programming techniques are concerned.

==Proposal details==
===Targeted breakthrough and its relevance towards a long-term vision===
====State of the art====
A few years ago the maximum processor clock frequency stopped at the level of about 3.5 GHz and is not increasing any more. The advances in performance of the processors are achieved by the means of architectural changes. Dual core processors are currently commonplace, and the multi-core architectures are getting larger and larger market share. On the other hand, the portable devices are becoming more and more powerful, with quad core ARM processors to enter the market by the end of 2012. However, in devices like mobile phones the energy efficiency becomes the primary objective. The energy dissipated in order to perform a specific operation is the most important figure of merit in such applications.
Reconfigurable computing is a new computing paradigm that bridges the gap between software and hardware. The reconfigurable hardware is perfectly matched to the computational requirements at the given time instant. It can be adapted to fulfil the demands of applications changing the functionality in every clock cycle.
Since the dynamic reconfiguration techniques have been discovered, and started to be supported by the commercially available FPGAs, different concepts of using them for computation acceleration have appeared. The dynamically reconfigurable resources were initially used as stand-alone coprocessors for demanding computations like image processing, data encryption, etc. Later, the development of nanometer CMOS technologies has allowed the implementation of sequential processors together with dynamically reconfigurable resources in a single die (system on chip). This technological progress allowed to develop a plenty of different concepts utilizing dynamically reconfigurable resources in computations and even in custom-made processors.
Some examples of reconfigurable architectures coupled more or less tightly with a classic processor are Chimaera, PRISC, OneChip, Chameleon and MOLEN. Some research groups invented systems that acted like independent processors but still needed some external control, like e.g. RaPiD (Reconfigurable Pipelined Datapaths). However, it suffered from limited bandwidth and performed well only in computationally intensive applications. PipeRench architecture is another example of such kind of system. It was able to execute some applications independently, but still needed a host processor for most of them. The architecture was composed of individually configurable pipeline stages. The executed application was first compiled into the set of virtual stages and then mapped onto physical stages in the chip.
Currently an active research is performed in the domain of Application-Specific-Instruction set-Processors (ASIPs), in which the pipeline structure can be customized and utilized in the program through custom instructions. An extension to this approach is the No-Instruction-Set-Computer (NISC). The NISC compiler maps the application directly to the datapath. The pipelined datapath structure remains constant throughout the entire execution of the program. Nevertheless the NISC compiler can obtain better parallelism and resource utilization than conventional instruction-set based compilers. This approach has allowed speedups of up to 70% compared to an instruction-set based compiler..
Integration of processor cores with reconfigurable resources opens issues regarding an OS (Operating System) dedicated for such solutions. BORPH – a slightly modified UNIX OS running on PowerPC of Virtex – allows programmers to treat the tasks implemented in the reconfigurable hardware in the same way as software tasks running on PowerPC. Nevertheless, developing a new or porting an existing application to use such a powerful architecture efficiently requires a quite low-level programming approach, which is far from current standards and trends.
Although none of the above-mentioned architectures managed to achieve a commercial success, reconfigurable computing remains a field of thorough research and commercial interest. It is worth emphasizing that in all of these architectures computation was distributed between a sequential processor and a FPGA coprocessor. The proposed solution in the RGPP is based on increasing the flexibility of the system by executing all the code only on dynamically reconfigurable fabric.
Objective
This proposal presents a completely new architecture of general purpose processor RGPP (Reconfigurable General-Purpose Processor), which does not have any fixed instructions and is based on the Dynamically Reconfigurable Field Programmable Gate Array (DFPGA). The processor is divided into several independently reconfigurable blocks called hardware partitions. The software code is partitioned and translated into optimized hardware representation instead of predefined (constant) set of assembly instructions. The proposed processor is being reconfigured on-the-fly in order to match the needs of the part of the program that is currently executed.
This alternative approach to a multi-core architecture allows the dynamically-controlled exploitation of fine-grained parallelism in standard software programs. The proposed architecture can be seamlessly integrated into the standard off-the-shelf computing hardware systems. The successful implementation of such an approach to a data processing may cause a revolution in the domain of the information and communication technologies (ICT) when the providers of personal and mobile computer platforms, such as Intel and AMD, realize the powerful features of the proposed solution.
The RGPP combines – in an unprecedented way – the idea of application-specific circuit with hardware virtualization achieved by means of self-managed dynamic reconfiguration. Besides of novel DFPGA architecture development, the realization of the RGPP project will come to fruition with a new software-to-hardware conversion technique, dedicated scheduling technique and some others algorithms supporting efficient reconfigurable computing.

====Feasiblity study====
The crucial question is: can a reconfigurable chip really achieve higher performance than a standard general-purpose processor? At first sight it seems improbable, as standard CPUs operate at much higher frequency and they do not suffer from reconfiguration overhead. However, there are two main sources of speedup in RGPP which may compensate for lower operating frequency and for the time needed for allocation (reconfiguration).
* on RGPP it should be possible to execute tasks faster on average (in terms of clock cycles) than on CPU due to the configurations optimized for each task
* on RGPP it should be possible to execute more tasks simultaneously than on CPU with comparable silicon area
The evaluation of RGPP performance and its comparison with conventional CPU is very difficult because it depends on many parameters of tasks to be executed and the manner in which both processors operate. Therefore, in order to roughly estimate the crucial parameters characterizing RGPP operation (reconfiguration time, maximal operating frequency, average resource usage per task, etc.), preliminary version of a custom configurable cell was proposed. Architecture based on this cell was compared with a six-core processor. For this purpose dedicated software was developed. It is able to simulate at an abstract level the execution of tasks on both CPU and RGPP. The software takes as an input several architectural parameters, simulates the execution of a randomly generated set of tasks and computes the average total execution time. A sample result of our study is presented in Figure 1.

[[Image:rgpp_vs_cpu.png|frame|center|Figure 1. RGPP vs. CPU comparison.]]

It was assumed that a classic processor is clocked 10 times faster than RGPP. The chart shows (see point A) that if we manage to achieve a 4x speedup in terms of clock cycles (k) in our RGPP chip and have enough resources to execute simultaneously 20 tasks on average, then the RGPP performance will be approximately equal to that of a CPU. Obviously, if higher level of parallelism or higher speedup is achieved, then RGPP will outperform classic processors. The preliminary tests of proposed reconfigurable cell indicate that achieving this goal is challenging, but feasible. Moreover, bearing in mind current publications on energy consumption of reconfigurable devices it is expected that RGPP-like architecture can be competitive also in this field. Therefore, the idea of reconfigurable computing as an alternative to general-purpose processor architectures used nowadays is certainly worth pursuing and more in-depth studies are needed to further evaluate its usefulness.
The RGPP approach has a potential to solve some of today’s problems with nanometer generation of multi-core sequential processors. The main problem that engineers and programmers need to cope with is extracting parallelism. Since increasing clock frequency became impossible due to its impact on power consumption, the performance of processors is increased by integrating more and more cores on a single chip. However, it is known that using the multi-core processors with more than eight cores will be inefficient because standard applications cannot be efficiently parallelized to make use of all the cores. This bottleneck should be eliminated in natural way with RGPP.
Furthermore, the proposed approach to processor architecture has the possibility to increase energy efficiency due to a fine-grained structure that allows flexible resource usage and deactivating idle partitions.
Another problem of today’s VLSI chips is the increasing rate of physical defects. Thanks to the RGPP’s architecture and its ability of reconfiguration, it allows implementation of a natural fault-tolerant mechanism. Moreover, defect-tolerating techniques are possible at very fine granularity. Without going into very technical details, this mechanism is based on the idea that the detected defective part is simply not used when the device is configured and, consequently, the chip operates correctly. The research and development of reconfigurable systems with their inherent fault-tolerance ability may help finding an efficient long-term solution for increasing chip manufacturing yield and contribute to further advance of microelectronics. Moreover, the environmental waste could be reduced by accepting as operational the integrated circuits with some faulty partitions. Due to a large amount of partitions, not all cells are required for normal operation of the processor. The faulty cells can be invalidated in similar way as in currently produced FLASH memories.
To conclude, the RGPP project results may bring milestones which will help in the development of self-contained reconfigurable systems. In the future, such systems due to their flexibility, easy fault-tolerance and the ability to naturally exploit parallelism may become a ground-breaking alternative to mainstream sequential processors. The successful completion of the project can strengthen the reconfigurable computing research network across Europe and ignite a worldwide industrial revolution.

===Novelty and foundational character===
The project is aimed at defining and prototyping non-conventional architecture of NISC (No-Instruction-Set Computer) processor, which implements paradigm very much different from any of the currently prevalent architectures such as CISC (Complex-Instruction-Set Computer), RISC (Reduced-Instruction-Set Computer) or VLIW (Very Long Instruction Word). Numerous attempts to develop similar architecture, none of which resulted in a wide adoption, prove that the research objective is valid and significant with respect to state of the art. The processing power of NISC is believed to significantly overcome currently available processors based on Von-Neumann or Harvard architecture.
To our best knowledge, the RGPP project is the first attempt to design the general purpose processor on the basis of fully reconfigurable hardware, without using any predefined hardware structures like datapaths. The proposed solution is an FPGA-based implementation of general-purpose processor, in which there are no sequentially executed instructions but all tasks are implemented in reconfigurable hardware, in a completely automatic way. The whole array of configurable blocks can be modified at runtime, except a small part responsible for reconfiguration management. The reconfigurable nature of RGPP allows the general purpose processor to adapt itself to the currently running software, thus maximally utilizing the underlying hardware, with advantages such as inherent parallelisation. Thus, RGPP exploits the parallelism of data processing and resources reuse of DFPGAs, without any limits on development of new applications nor exploiting the existing ones.

===S/T methodology===
There are several technical issues that need to be addressed during the project realization. Some of them are briefly described below.
====Concurrency====
Bearing in mind that the proposed processor is intended to be of general purpose, it should be able to execute any user application. Note that the processor will be a kind of dynamically reconfigurable FPGA, without typical hard- or soft- processor core, like in most custom reconfigurable systems. Applications to be executed should be stored in a memory as a set of bitstreams, which provide required functionality, when loaded into DFPGA in a correct sequence. The same must apply to the operating system, shared libraries, interrupt handlers, drivers, etc. Each bitstream must be loaded into DFPGA on demand, when operations corresponding to this bitstream should be performed now or in the near future. When the operations being performed by a given part of DFPGA are finished, this part can be configured with a different bitstream, serving a new functionality. This means that the DFPGA should be partially reconfigurable and should support very efficient reconfiguration techniques.
Devoting a part of FPGA for each thread allows running many threads concurrently, without time-division technique (Figure 2). Obviously, similar acceleration is obtained in multi-core, traditional processors, but proposed approach is much more flexible and scalable.

[[Image:rgpp_conc_thread_exec.png|frame|center|Figure 2. Concurrent thread executions.]]

To manage the thread executions (in other words: to load the required bitstreams into the proper FPGA partitions) a special Control Unit is required. This block is the only static module in the FPGA – its configuration cannot be modified at runtime. The required dependencies between bitstreams should be determined during the bitstream set generation process and stored – together with these bitstreams – in memory. The control block can only suspend a thread execution if there is no place for loading of the new bitstream.
====Plasticity====
The functionality of most threads is too complex to be implemented directly in the DFPGA. Therefore they must be split into the sequence of smaller pieces – partitions. The partitions can be in turn composed of several sub-units – operations, optionally finished with a jump. The exact definition of the operation constitutes an open issue and will be elaborated by means of some experiments.
In order to obtain a satisfying flexibility, it should be possible to place the partitions in any part of the FPGA. It means that the current, commercially available reconfiguration techniques, due to their limitations, cannot be efficiently used for this purpose (e.g., such techniques provided by Xilinx require the dynamic partition to be placed in a predefined area corresponding to one clock region). Therefore, in the project a completely new custom reconfigurable architecture providing the necessary reconfiguration flexibility, dedicated to the specific project requirements, will be designed.

====Impact on software development====
The crucial point of the proposed general-purpose reconfigurable processor is an automatic transformation of any software operation into the dedicated, optimized hardware partition – this optimisation constitutes the main source of potential processing speedup. Assuming that the thread to be partitioned is specified by means of any high-level programming language, e.g. C++, it can be converted to a set of corresponding bitstreams in different ways. There are many projects, based on C++ to HDL conversion, but since this problem is complex, the results of these projects are still limited to fractions of C++ standard and therefore are not suitable for general-purpose processor implementation. Our novel approach is composed of three phases: C++ to an intermediate code conversion, partitioning and finally synthesis. Such a method, based on intermediate program representation seems to be much more efficient. The main advantage is the use of advanced front-end tools existing in e.g. a GNU Compiler, for reduction of complex, high-level programming structures to simple intermediate code.
New processor architecture would be incomplete without a dedicated operating system (OS). Traditionally, an operating system is responsible for memory management, interrupts and hardware control, scheduling and inter-process communication (IPC). Many operating systems have common programming interface and it is possible to run an application written on one OS on a different OS. The most known operating system interface is POSIX (Portable Operating System Interface) derived from Unix family. The operating system for the NISC processor should also have this interface to make the application development independent from the underlying system architecture.
Proposed platform drastically differs from platforms based on the commonly used processors (RISC or CISC), thus the architecture of its OS will be much different from already known ones. The required OS will not manage applications written for the sequential processor but will load the bitstreams corresponding to applications. This issue changes the way in which programs will be run and how the OS will manage them. The OS has to manage partition bitstreams to satisfy the condition of existence of all required functionality (implemented in particular bitstreams) at a given time. Hence, the process of scheduling is more complex than on a typical RISC or CISC processor. Therefore, the OS needs to provide explicit functionality to:
* loading and unloading partition bitstreams
* scheduling partitions to fully utilize the reprogrammable array
* arranging the communication channels between partitions if needed
* serializing memory accesses

====Challenges====
As there are no solutions which might be considered the ultimate NISC architecture, the actual work carried out during realization of the project will have exploratory and risky character. The outcome of work will detail the completely new architecture and lay out the formal description of the resulting system behaviour. Given the extent of the expected functionality, which in effect shall allow the RGPP to be used in general purpose applications, the research scope goes beyond any of the currently running projects. Due to the complexity of the processor, efficient methods of emulation need to be defined, which will require an innovative approach in order to make the system simulations feasible for functional verification. The general purpose applications of the RGPP require special handling both at the compiler level, which creates the program in a form suitable for execution on the processor, and the OS level, which traditionally provides facilities and methods of accessing and sharing the system (main processor and devices). The work on compiler will be focused on methods of efficient translation of given high-level program to applicable bitstream, which due to the conceptual level of execution (direct execution on FPGA, rather than on a CPU which hides the details of the processor implementation), has not been widely explored.
Despite its risky character, the proposed research has the potential of changing the current thinking about general purpose processors.
====The interdisciplinary team====
The project idea constitutes a fresh mixture of insights from various disciplines. The project scope includes development of software tools (compilers, OS, emulators) together with a silicon demonstrator that will exercise some aspects of dynamic reconfiguration. The project team consists of experts from different fields (reconfigurable computing, processor architectures, VLSI design, high-level hardware compilers, programming languages, operating systems, etc.), which in connection with the specific work plan guarantees high level of synergy and increase in the overall efficiency of the group. The team members involved in different workpackages at the same time may get a unique opportunity to exchange ideas at different stages of the project. In particular, experiences from hardware implementation or system architecture can contribute significantly to the dedicated operating system and the compiler development. This course of action is expected to result in a more robust and reliable system. The complementarity of the team should permit to apply cutting-edge VLSI techniques to advanced dynamic reconfigurable architectures, enveloped with a programming interface that will allow programmers to easily exploit the high-performance computing capabilities offered by the reconfigurable platform.
The project touches several research areas of general interest (software to hardware conversion, parallelisation of calculations, efficient dynamic reconfiguration, and dedicated operating system). Therefore even if the final goal will not be achieved or some partial results will not be satisfactory, the project can produce many interesting outcomes and conclusions for the future.

Polish National Science Centre project 2011/01/N/ST7/05242

Pamrozik — Thu, 30 Jan 2014 18:31:02 GMT

Summary:

==Call description==
The project proposal was submitted for Polish National Science Centre call [http://www.ncn.gov.pl/finansowanie-nauki/konkursy/typy/2?language=en PRELUDIUM 1]. This call type is addressed to young researchers who does not have a doctoral degree. The proposal must involve [http://www.ncn.gov.pl/sites/default/files/pliki/ustawy/ustawa-o-finansowaniu-nauki.pdf basic research].

==Team members==
{|
|-
|style="width: 85px"|[[Image:pamrozik.jpeg|80px|frameless|border]]
|
'''Piotr Amrozik, PhD'''<br>
phone: +48 (42) 631 27 22<br>
e-mail: pamrozik@dmcs.pl<br>
[http://www.linkedin.com/pub/piotr-amrozik/2/340/1b Detailed information]
|}
Role in the project: '''principal investigator'''.

{|
|-
|style="width: 85px"|[[Image:napier.jpeg|80px|frameless|border]]
|
'''Prof. Andrzej Napieralski'''<br>
phone: +48 (42) 631 26 45<br>
e-mail: napier@dmcs.pl<br>
[http://www.napieralski.dmcs.pl/en/index.php Detailed information]
|}
Role in the project: '''supervisor'''.

==Proposal details==
Project proposal entitled "Microarchitecture of computational elements for general purpose reconfigurable processor" was submitted to Polish National Science Centre on 14th of June 2011. It had been accepted and qualified for funding. The project started on 21st of December 2011 and ended on 20th of December 2013.

===Project scientific goal===
<div class="center" style="width: auto; margin-left: auto; margin-right: auto;">''The main goal of the project is research on the modular dynamically reconfigurable microarchitectures due to their possible application in a general purpose microprocessor, which can break today’s paradigm of sequential thread execution in the fixed hardware resources.''</div>

The final result of the proposed project is aimed at extending the current knowledge on computer architecture hardware resources. To achieve this goal, besides the theoretical research on the new dynamically reconfigurable architecture of the general purpose processor, possibilities and constraints of its implementation in one of the up-to-date microelectronics technologies must be analysed as well.

===Concept and plan of the research===
The state of the art preview shows a great potential of dynamically reconfigurable devices to substitute, in near time, the nowadays processor architectures. Due to their specific features, it is not enough to propose only the novel architecture, which is expected to give better results in theory. There is a need of research on the solution which will be able to address known issues regarding dynamically reconfigurable devices, using a completely new approach to the current computing circuit implementation paradigms. Therefore, the realization of the project requires physical synthesis allowing designation of the actual capabilities of proposed circuit. Actually, proposed project constitutes joint research on fundamental computer architecture and on possibilities of utilizing it in a real device.

As it was mentioned earlier, within the confines of this project, the research on a possible usage of the modular multi-context dynamically reconfigurable microarchitecture as a general purpose microprocessor will be performed. During this research, the following aspects regarding the architecture will be considered:
* dynamic reconfigurability of the circuit – this research will have direct impact on the flexibility and the speed of the circuit reconfiguration
* multi-context reconfigurability with emphasis on data sharing between contexts – multi-context reconfiguration increases flexibility of usage of the resources and can help to decrease the number of required reconfigurations during a run-time
* configuration memory – multi-context techniques implementation requires a large amount of resources for a configuration memory. Therefore, the full-custom design approach will be considered in order to reduce the occupied area
* computing unit architectures – during this research multiple arithmetic architectures will be explored to check for those which can give advantageous realisation in proposed modular architecture
* matrix granularity – it is important due to the usability of the device and has a direct impact on the size of required bitstreams and configuration method
* internal connection interfaces – important due to the need of a flexible exploitation of hardware resources by tasks to be performed
* memory interface – large number of parallel tasks will require well organized access to data from a memory what requires the research on a alternative solutions in respect to the ones in nowadays microprocessor architectures
The proposed architecture will be described in hardware description language VHDL and synthesized with one of the newest VLSI digital technologies. The verification of the theoretical assumptions will be performed through back-annotated post-layout simulations of proposed circuit.

===Research methodology===
Realisation of the project will be conducted in three steps:
#Architecture research and implementation: firstly, the author will search for possible circuit realisations and secondly the description of the proposed architecture will be prepared using VHDL hardware description language.
#Logic and physical synthesis of the device: this step will be based on the author’s current doctoral thesis which concerns the modular dynamically reconfigurable device design methodology.
#Verification: consists of evaluation of the basic features of the device: e.g. reasonable number of computing units (depends on chosen technology), reconfiguration speed, size of a bitstream, possible processing speed, etc. All this will be acquired by back-annotated post-layout simulations.

==Results==

===Main achievements of the project===

# Development of general purpose processor architecture based on dynamically reconfigurable resources without employing fixed cores and their commonly used hardware like ALU or processor registers, and in particular:
#* development of flexible configuration method of CLB,
#* development of partition activation and deactivation mechanism,
#* development of matrix of CLB architecture supporting computations on 32/64-bit operands,
#* development of interface to access the partition to the memory.
# Realisation of the project resulted in two patent applications that were submitted to Polish Patent Office.
# Implementation of the developed processor in [http://www.tsmc.com/english/dedicatedFoundry/technology/65nm.htm TSMC 65 nm technology process].
# The processor was roughly compared in terms of performance with other commercially available architectures and obtained result confirmed usability of the new architecture.

===Realisation of the scientific goals - summary===
All goals assumed in the project proposal were achieved. The details about the goals and they realisation is presented in table 1.
During project realisation one additional goal had been realised, namely consistent and automated design environment dedicated to design of modular dynamically reconfigurable devices had been developed. This environment considerably speeded-up realisation of the reconfigurable processor architecture.

{| class="wikitable"
|+ Table 1. Realisation of the assumed goals.
! Assumed goals
! Realisation status
|-
| Research on a modular dynamically reconfigurable microarchitecture to determine whether it can be used as general purpose processor, in particular:
|-
|
* employing multi-context dynamical reconfiguration with special consideration of data exchange between context,
| '''Achieved:''' development of dynamically reconfigurable matrix of CLB supporting multi-context data exchange and the mechanism of partition activation and deactivation (subject of patent).
|-
|
* development of computational elements architecture, selection of matrix granularity, development of internal connection interfaces,
| '''Achieved:''' development of flexible CLB architecture supporting computations on 32/64-bit operands.
|-
|
* development of memory access interface,
| '''Achieved:''' development of interface to access the partition to memory.
|-
|
* device implementation with one of the newest technology process,
| '''Achieved:''' the device was implemented in TSMC 65 nm, automated implementation flow was developed.
|-
|
* realisation of post-layout simulations, and utilisation of obtained results to research on architecture and to comparison to typical processor architectures.
| '''Achieved:''' post-layout simulations of the device confirming its correct operation was realised. Obtained results were used as a feedback to the research on the processor architecture and its comparison.
|}

Polish-Swiss Research Programme 2010

Pamrozik — Thu, 30 Jan 2014 17:47:36 GMT

Summary: Proposal description for Polish-Swiss research programme

==Proposal details==
===Justification of the project’s realisation===
A few years ago the maximum processor clock frequency has stopped at the level of about 3.5 GHz and is not increasing any more. The advances in performance of the processors are achieved by the means of architectural changes. The dual core processors are currently commonplace, and the multicore architectures are getting larger and larger market share. On the other hand, the portable devices are becoming more and more powerful, with the dual core ARM processors entering the market at the moment, but the energy efficiency is the primary factor in their usefulness. The energy dissipation per the unit of work performed is a figure of merit in such applications.
In this proposal a new architecture of general purpose processor, which does not have any fixed instructions and is based on the Dynamically Reconfigurable Field Programmable Gate Array (DFPGA) is presented. It is an alternative approach to a multicore architecture, allowing the dynamically-controlled exploitation of fine-grained parallelism in standard software programs. Fine-grained resource management could also reduce the energy consumption by not providing power to the partitions which are currently not used. This architecture can be seamlessly integrated with the standard off-the-shelf computing hardware systems. The successful implementation of such an approach to a data processing may cause a revolution in the domain of the information and communication technologies (ICT) when the providers of personal and mobile computers, such as Intel and AMD, realize the powerful features of the proposed solution.
The ICT region constitutes a very important part of European Union economy. According to The 2010 report on R&D in ICT in the European Union [1] it is major sector in terms of R&D costs and labour productivity playing a significant role in the overall EU economy. In case of Poland, taking into account the manufacturing sub-sector of ICT, one can observe a significant increase in employment over last few years (up to 4.2% of the EU total). However, considering other figures of merit, it becomes quite obvious that development of countries like Poland, Hungary and Czech Republic is based on rather lower-end activities. Projects like REuP is believed to contribute drastically to the process of increasing inventiveness of the Polish economy by stimulating creation of R&D centres and attracting foreign capital from this field.
The realization of this project will allow to enhance the links between Technical University of Lodz and Haute Ecole d'Ingénierie et de Gestion du Canton de Vaud (HEIG-VD) acquired during the successful realization of the EU FP6 project PERPLEXUS. The results of the REuP project can provide a solid foundation for a future research in the domain of reconfigurable computing.

[1] G. Turlea, D. Nepelski, G. de Prato, S. Lindmark, A. de Panizza, L. Picci, P. Desruelle, D. Broster, "The 2010 Report on R&D in ICT in the European Union", ISBN 978-92-79-15542-0, European Union, 2010 (available from http://ftp.jrc.es/EURdoc/JRC57808.pdf)

===Scientific Quality===
Since the dynamic reconfiguration techniques have been invented and become available in the commercial FPGAs, different concepts of using them for acceleration of many types of computations have appeared. The dynamically reconfigurable resources were initially used as stand-alone coprocessors for demanding computations like image processing, data encryption, etc. Later, the development of nanometer CMOS technologies has allowed to implement the sequential processors together with dynamically reconfigurable resources in a single die (system on chip). This technological progress allowed to develop a plenty of different concepts utilizing dynamically reconfigurable resources in computations and even in custom-made processors [1], [2], [13], [14].
Some examples of reconfigurable architectures coupled more or less tightly with a classic processor are Chimaera [7], PRISC [8], OneChip [9], Chameleon [10] and MOLEN [12]. Some research groups invented systems that acted like independent processors but still needed some external control, like e.g. RaPiD (Reconfigurable Pipelined Datapaths) [11]. However, it suffered from limited bandwidth and performed well only in computationally intensive applications. PipeRench [5] architecture is another example of such kind of system. It was able to execute some applications independently, but still needed a host processor for most of them. The architecture was composed of individually configurable pipeline stages. The executed application was first compiled into the set of virtual stages and then mapped onto physical stages in the chip.
Currently an active research is performed in the domain of Application-Specific-Instruction set-Processors (ASIPs), in which the pipeline structure can be customized and utilized in the program through custom instructions. An extension to this approach is the No-Instruction-Set-Computer (NISC). The NISC compiler maps the application directly to the datapath [4]. The pipelined datapath structure remains constant throughout the entire execution of the program. Nevertheless the NISC compiler can obtain better parallelism and resource utilization than conventional instruction-set based compilers.
Although none of above-mentioned architectures managed to achieve a commercial success, reconfigurable computing remains a field both of research and commercial interest. It is worth emphasizing that in all of these architectures the computations were distributed between a sequential processor and a FPGA coprocessor. The solution proposed in the REuP is based on increasing the flexibility of the system by executing all the code only on dynamically reconfigurable fabric. Therefore, the control module needs to be responsible only for managing the bitstreams and configuration of partitions and remains the only static part of the system.
The REuP is a direct continuation of the NISC idea, extended with the possibility of dynamic datapath modification and hardware virtualization achieved by means of self-managed dynamic reconfiguration [5]. Besides of novel DFPGA architecture development, the realization of the REuP project will provide new compilation techniques, specialized physical synthesis tools and dedicated scheduling algorithms.
Another problem of today’s VLSI chips is the increasing rate of defects. The REuP’s architecture and its ability of reconfiguration allow implementing a natural fault-tolerant mechanism at fine granularity. The defective partitions are simply not used when the device is configured and, consequently, the program operates correctly. The research and development of reconfigurable systems with their inherent fault-tolerance ability may help finding an efficient long-term solution to chip defects [6].
Integration of processor cores with reconfigurable resources opens issues regarding an OS (Operating System) dedicated for such solutions. In [3] a slightly modified UNIX OS running on PowerPC of Virtex allows programmers to treat the tasks implemented in the reconfigurable hardware in the same way as software tasks running on PowerPC. Developing a new or porting an existing application to use such powerful architecture efficiently requires a quite low-level programming approach, which is far from current standards and trends. This is one of very important challenges that will have to be overcome.
The results of the REuP project (C-to-VHDL compiler, processor architecture with custom dynamic reconfiguration techniques, physical synthesis tool, dedicated OS, system emulator) may become a milestone which will help in the development of self-contained reconfigurable systems. In the future, such systems due to their flexibility, fault-tolerance and the ability to naturally exploit parallelism may become a revolutionary alternative to mainstream sequential processors.

[1] M. Chmiel, J. Mocha, D.Kania, E. Hrynkiewicz, „Dynamic partial reconfiguration of CPU-s for Programmable Logic Controllers executing control programs developed in the Ladder Diagram language”, DESDes 2009, Valencia, Spain, October 2009
[2] S. Banerjee, E. Bozorgzadeh, N Dutt, “Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 234-247, San Francisco, CA, USA, February 2009
[3] H. K.-H. So, R. Brodersen, “A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH”, Transactions on Embedded Computing Systems, vol. 7(2), pp 1-28, February 2008
[4] M. Reshadi, B. Gorjiara, D. Gajski, “Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths”, Proceedings of the 2005 International Conference on Computer Design, pp. 69-76, San Jose, CA, USA, October 2005
[5] H. Kagotani, H. Schmit, “Asynchronous PipeRench: Architecture and Performance Evaluations”, Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’03), Napa, CA, USA, April 2003
[6] Collet J.H., Psarakis M., Zając P., Gizopoulos D., Napieralski A.; “Comparison of Fault-Tolerance Techniques for Massively Defective Fine- and Coarse-Grained Nanochips”, 16th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2009, pp. 23-30, Lodz, Poland 25-27 June 2009
[7] Z. A. Ye, A. Moshovos, S. Hauck, P. Banerjee. CHIMAERA: A high-performance architecture with a tightly coupled reconﬁgurable functional unit. Proceedings of the 27th International Symposium on Computer Architecture, June 2000.
[8] R. Razdan, M. Smith. A high-performance microarchitecture with hardware-programmable functional units. Proceedings of the 27th Annual IEEE/ACM International Symposium on Microarchitecture, November 1994
[9] J. E. Carrillo, E. P. Chow. The effect of reconﬁgurable units in superscalar processors. Proceedings of the Ninth ACM International Symposium on Field-Programmable Gate Arrays, February 2001.
[10] D. Wilson. Chameleon takes on FPGAs, ASICs. Electronic Business Asia, EDN Online Magazine (http://www.edn.com/article/CA50551.html?partner=enews), October 2000
[11] D. Cronquist, P. Franklin, C. Fisher, M. Figueroa, C. Ebeling. Architecture design of reconﬁgurable pipelined datapaths. Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI, March 1999
[12] S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov, E.M. Panainte, “The MOLEN polymorphic processor”, IEEE Transactions on Computers, vol.53, no.11, pp. 1363- 1375, Nov. 2004
[13] C. Paiz, T. Chinapirom, U. Witkowski, M. Porrmann, "Dynamically Reconfigurable Hardware for Autonomous Mini-Robots," Conference on IEEE Industrial Electronics, IECON 2006 - 32nd Annual, vol., no., pp.3981-3986, 6-10 Nov. 2006
[14] Zexin Pan, B. Earl Wells, "Hardware Supported Task Scheduling on Dynamically Reconfigurable SoC Architectures," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, no.11, pp.1465-1474, Nov. 2008

===Innovative character===
The project is aimed at defining and prototyping architecture of NISC processor, which implements paradigm very much different from any of the currently prevalent architectures such as CISC, RISC or VLIW. Numerous attempts to develop similar architecture, none of which resulted in a wide adoption, prove that the research objective is valid and significant with respect to state of the art.
To our knowledge, the REuP project is the first attempt to design the general purpose processor on the basis of fully reconfigurable hardware, without using any predefined hardware structures like datapaths. The proposed solution is an FPGA-based implementation of general-purpose processor, in which there are no sequentially executed instructions but all tasks are implemented in reconfigurable hardware, in a completely automatic way. The whole array of configurable blocks can be modified at runtime, except for a small part responsible for reconfiguration management. The reconfigurable nature of REuP allows the general purpose processor to adapt itself to running particular software, thus maximally utilizing the underlying hardware, with advantages such as inherent parallelisation. Thus, REuP exploits the parallelism of data processing and resources reuse of DFPGAs, without any impact on development of new applications nor the existing ones.
Bearing in mind that the proposed processor is intended to be a general-purpose one, it should be able to execute any user application. Note that the processor will be a kind of fully reconfigurable FPGA, without typical hard- or soft- processor core, like in most custom reconfigurable systems. Applications to be executed should be stored in a memory as a set of bitstreams, which provide required functionality, when loaded into FPGA in a correct sequence. The same must apply to the operating system, shared libraries, interrupt handlers, drivers, etc. Each bitstream must be loaded into FPGA on demand, when operations corresponding to this bitstream should be performed now or in the near future. When the operations being performed by a given part of FPGA are finished, this part can be configured with a different bitstream, serving a new functionality. This means that the FPGA should be partially reconfigurable and should support very efficient reconfiguration techniques.
Devoting a part of FPGA for each thread allows running many threads concurrently, without time-division technique. Obviously, similar acceleration is obtained in multi-core, traditional processors, but proposed approach is much more flexible and scalable.
The functionality of most threads is too complex to be implemented directly in the DFPGA. Therefore it must be split into the sequence of smaller pieces – partitions. The partitions can be in turn composed of several sub-units – operations, optionally finished with a jump. The exact definition of the operation constitutes an open issue and will be elaborated by means of some experiments.
In order to obtain the satisfying flexibility, it should be possible to place the partitions in any part of the FPGA. It means that the current, commercially available reconfiguration techniques, provided e.g. by Xilinx, cannot be efficiently used for this purpose. These techniques require the dynamic partition to be placed in a predefined area, surrounded with special communication blocks (Bus Macros) providing a predefined IO interface. Therefore, a completely new custom reconfigurable architecture will be designed providing the necessary reconfiguration flexibility.
The crucial point of the proposed general-purpose reconfigurable processor is an automatic transformation of any software operation into the hardware partition. Assuming that the thread to be partitioned is specified by means of any high-level programming language, e.g. C++, it can be converted to a set of corresponding bitstreams in different ways. There are many projects, based on C++ to HDL conversion [3][4], but since this problem is complex, the results of these projects are still limited to fractions of C++ standard and therefore are not suitable for general-purpose processor implementation. Our novel approach is composed of three phases: C++ to an intermediate code conversion, partitioning and finally synthesis. Such a method, based on intermediate program representation seems to be much more efficient. The main advantage is the use of advanced front-end tools existing in e.g. a GNU Compiler, for reduction of complex, high-level programming structures to simple intermediate code.
New processor architecture would be incomplete without a dedicated operating system. Traditionally, an operating system is responsible for memory management, interrupts and hardware control, scheduling and inter-process communication (IPC). Many operating systems have common programming interface and it is possible to run an application written on one OS on a different OS. The most known operating system interface is POSIX (Portable Operating System Interface) derived from Unix family. The operating system for the instructionless processor, called BitstreamOS, should also have this interface to make the application development independent from the underlying system architecture.
Proposed platform differs significantly from platforms based on the commonly used processors (RISC or CISC), thus the architecture of BitstreamOS will be different from known operating systems. BitstreamOS will not manage applications written for the sequential processor but will load the bitstreams corresponding to applications. This issue changes the way in which programs will be run and how the BitstreamOS will manage them. BitstreamOS has to manage partition bitstreams to satisfy the condition of existence of all required functionality (implemented in particular bitstreams) at a given time. Hence, the process of scheduling is more complex than on a typical RISC or CISC processor. Therefore, BitstreamOS needs to provide explicit functionality to:
* loading and unloading partition bitstreams
* scheduling partitions to fully utilize the reprogrammable array
* arranging the communication channels between partitions if needed
* serializing memory accesses
As there are no solutions which might be considered the ultimate NISC architecture, the actual work carried out during realization of the project will have exploratory character. The outcome of work will detail the new architecture and lay out the formal description of the resulting system behaviour. Given the extent of the expected functionality, which in effect shall allow the REuP to be used in general purpose applications, goes beyond any of the currently running projects. Due to the complexity of the processor, an efficient methods of emulation need to be defined, which will require an innovative approach in order to make the system simulations feasible for verification of functionality. The general purpose applications of the REuP require special handling both at the compiler level, which creates the program in a form suitable for execution on the processor, and the OS level, which traditionally provides facilities and methods of accessing and sharing the system (main processor and devices). The work on compiler will be focused on methods of efficient translation of given high-level program to applicable bitstream, which due to the conceptual level of execution (direct execution on FPGA, rather than on a CPU which hides the details of the processor implementation), has not been widely explored.

===Consortium===
[[Polish-Swiss Research Programme team|Members of consortium created for the application.]]

Project funding

Pamrozik — Thu, 30 Jan 2014 17:40:54 GMT

Summary:

The project's authors have submitted several applications for funding to various research programmes since 2010. Below, the short history and some proposal details are presented:
*[[Polish-Swiss Research Programme 2010|Polish-Swiss Research Programme]] - proposal submitted in July 2010 and rejected.
*[[Polish National Science Centre project 2011/01/N/ST7/05242|Polish National Science Centre project]] - proposal submitted in June 2011 and '''accepted in December 2011'''. Reference number: 2011/01/N/ST7/05242.
*[[UE 7FP ICT FET Open project]] - proposal submitted in September 2012 and rejected.